Assign a synthesizable initial value to a reg in Verilog

Question

I'm an FPGA noob trying to learn Verilog. How can I "assign" a value to a reg in an always block, either as an initial value, or as a constant. I'm trying to do something like this in the code below. I get an error because the 8 bit constant doesn't count as input. I also don't want to trigger the always off of a clock. I just want to assign a register to a specific value. As I want it to be synthesisable I can't use an initial block. Thanks a lot.

module top
(
    input wire clk,
    output wire [7:0] led   
 );


reg [7:0] data_reg ; 
always @*
begin
    data_reg = 8'b10101011;
end

assign led = data_reg;

endmodule

score 36 · Accepted Answer · answered Apr 04 '12 at 17:48

36

You can combine the register declaration with initialization.

reg [7:0] data_reg = 8'b10101011;

Or you can use an initial block

reg [7:0] data_reg;
initial data_reg = 8'b10101011;

answered Apr 04 '12 at 17:48

Nathan Farrington

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@Tim Also works in Quartus synthesizing for Altera's Cyclone II. – Roman Starkov Apr 28 '13 at 00:39
@NathanFarrington is it possible to initialize the reg with a variable (say a input parameter of the module). I tried doing it directly as above but it doesn't work.. – ishan3243 Nov 14 '13 at 19:59
@anonymous It is possible to initialize a reg with a parameter, but not a regular input. – alex.forencich Nov 16 '13 at 02:07
Will this synthesize? – augurar Feb 19 '14 at 21:51
It depends on your synthisis tool vendor, version and settings. Traditionally synthisis tools ignored initial conditions but some now support them. – plugwash Nov 18 '15 at 16:04
I’m confused. The way I know of doing it is using the reset line. Can you add a source for this? – JobHunter69 Jul 15 '19 at 23:11

score 6 · Answer 2 · answered Apr 04 '12 at 20:47

You should use what your FPGA documentation recommends. There is no portable way to initialize register values other than using a reset net. This has a hardware cost associated with it on most synthesis targets.

Morgan · Answer 3 · 2012-04-04T08:03:07.270

The always @* would never trigger as no Right hand arguments change. Why not use a wire with assign?

module top (
    input wire clk,
    output wire [7:0] led   
);

wire [7:0] data_reg ; 
assign data_reg   = 8'b10101011;
assign led        = data_reg;

endmodule

If you actually want a flop where you can change the value, the default would be in the reset clause.

module top
(
    input        clk,
    input        rst_n,
    input  [7:0] data,
    output [7:0] led   
 );

reg [7:0] data_reg ; 
always @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    data_reg <= 8'b10101011;
  else
    data_reg <= data ; 
end

assign led = data_reg;

endmodule

Hope this helps

Mark Lakata · Answer 4 · 2019-04-10T21:25:18.320

5

The other answers are all good. For Xilinx FPGA designs, it is best not to use global reset lines, and use initial blocks for reset conditions for most logic. Here is the white paper from Ken Chapman (Xilinx FPGA guru)

http://japan.xilinx.com/support/documentation/white_papers/wp272.pdf

edited Apr 10 '19 at 21:25

answered Mar 18 '14 at 17:32

Mark Lakata

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That isn't what KC's paper says. He just says that reset lines can be expensive, and you should think about whether each part of the design actually needs to be reset, given that it might quickly clock out of an unknown state, or might not be implementable with a reset (an SRL16, for example). It is absolutely the wrong conclusion that you should avoid explicit reset lines. – EML Apr 03 '19 at 19:46
I updated my answer to use the word **global**. KC clearly says global reset lines are bad (expensive, time consuming and unnecessary), and that reset circuitry should only be used where necessary. – Mark Lakata Apr 10 '19 at 21:26

score 4 · Answer 5 · answered Apr 04 '12 at 07:08

4

When a chip gets power all of it's registers contain random values. It's not possible to have an an initial value. It will always be random.

This is why we have reset signals, to reset registers to a known value. The reset is controlled by something off chip, and we write our code to use it.

always @(posedge clk) begin
    if (reset == 1) begin // For an active high reset
        data_reg = 8'b10101011;
    end else begin
        data_reg = next_data_reg;
    end
end

answered Apr 04 '12 at 07:08

Paul S

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What you say is true for ASICs in general but not for FPGAs specifically. When you download the bitfile, all memory cells are initialized. Resets are often not needed or helpful for FPGA-based designs, and lead to larger area and possibly lower Fmax. The best reset is downloading the bitfile again. – Nathan Farrington Apr 04 '12 at 17:44
@NathanFarrington Thanks. I've got a similar issue I'm trying to understand. I have a state register for a FSM that doesn't seem to initialize unless I assign it to drive an output wire. I opened another post [link](http://stackoverflow.com/questions/10033459/verilog-fpga-use-of-an-unitialized-register). The behavior seems to be related to what we're discussing here. Maybe you could check it out and tell me what you think. It's Verilog coded targeting Xilinx FPGA. Thanks – Frank Dejay Apr 05 '12 at 18:01

Assign a synthesizable initial value to a reg in Verilog

5 Answers5