What are the codes such as CC, LD and CC[M] output when compiling the Linux kernel?

Question

While compiling Linux from scratch I realize that there are compile codes that appear while compiling.

For example CC filename , LD filename, CC[M] filename.

What do these codes mean?

Answer 1

The different markings specify the following

• [CC] - Compiles the C file into an designated object file. The object file contains the archicture assembler code of that .c file. As it might also reference parts outside its scope. For example calling another function in another .c file. The function calls are left open within the object file, which is later included by the linker. Therefore
• [LD] is the proces of linking the compiled objects together, and wire up the function calls that has been left open by the compiler. However, many parts are linked together as the core part of the kernel, while some parts are left out. And thus you see
• [CC (M)] for those parts which are compiled as points to be loaded into the kernel at runtime. But which are not linked together in the monolithic part of the kernel. But instead can be inserted when the kernel is booted.

Answer 2

Let's take an specific example and figure out what it does in the kernel 4.1, e.g. IHEX.

Find what a code does

Just run:

make SHELL='sh -x'

How that works: https://stackoverflow.com/a/32010960/895245

If we grep the output for IHEX, we find the lines:

+ echo   IHEX    firmware/e100/d101s_ucode.bin
  IHEX    firmware/e100/d101s_ucode.bin
+ objcopy -Iihex -Obinary /home/ciro/git/kernel/src/firmware/e100/d101s_ucode.bin.ihex firmware/e100/d101s_ucode.bin

so we conclude that IHEX does a objcopy -Iihex.

Find where a code is defined

Every kernel command must be defined with something like:

quiet_cmd_ihex  = IHEX    $@
      cmd_ihex  = $(OBJCOPY) -Iihex -Obinary $< $@

$(obj)/%: $(obj)/%.ihex
        $(call cmd,ihex)

for the verbosity settings (e.g. V=1 and make -s) to work.

So in general, you just have to

git grep 'cmd.* = CODE'

to find CODE.

I have explained in detail how this system works at: https://stackoverflow.com/a/32023861/895245

Get the list of all codes

make | grep -E '^  ' | sort -uk1,1

CC and CC [M]

Defined in scripts/Makefile.build:

quiet_cmd_cc_o_c = CC $(quiet_modtag)  $@
      cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<

and the [M] comes from the target specific variables:

$(real-objs-m)        : quiet_modtag := [M]
$(real-objs-m:.o=.i)  : quiet_modtag := [M]
$(real-objs-m:.o=.s)  : quiet_modtag := [M]
$(real-objs-m:.o=.lst): quiet_modtag := [M]
$(obj-m)              : quiet_modtag := [M]

It is then called through:

$(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE
    [...]
    $(call if_changed_rule,cc_o_c)

define rule_cc_o_c
    [...]
    $(call echo-cmd,cc_o_c) $(cmd_cc_o_c);                \

where if_changed_rule is defined in scripts/Kbuild.include as:

if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ),                 \
    @set -e;                                                             \
    $(rule_$(1)))

and Kbuild.include gets included on the top level Makefile.

LD

There are a few versions, but the simplest seems to be:

quiet_cmd_link_o_target = LD      $@
cmd_link_o_target = $(if $(strip $(obj-y)),\
              $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \
              $(cmd_secanalysis),\
              rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@)

$(builtin-target): $(obj-y) FORCE
    $(call if_changed,link_o_target)

and in scripts/Kbuild.include:

# Execute command if command has changed or prerequisite(s) are updated.
#
if_changed = $(if $(strip $(any-prereq) $(arg-check)),                       \
    @set -e;                                                             \
    $(echo-cmd) $(cmd_$(1));                                             \
    printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)

Answer 3

It should show:

• CC when compiling a core part of the kernel
• CC [M] when compiling a module
• LD when linking