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I am getting above error while running modelsim on a VHDL Testcase and I am unable to understand why is it an error.

The Testcase:

LIBRARY IEEE;
Use ieee.std_logic_1164.all;

entity a is
port (in11 : in std_logic
);
end a;

Architecture a of a is:

component b_1 
 port ( in1 : in bit);
end component;


begin
   inst : b_1 port  map ( in1=> **to_Bit**(in11));
end a;
toolic
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Dharmendra
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2 Answers2

4

That's a modelsim error, actually it should report that you are not allowed to use this function as actual in a port map, this works:

LIBRARY IEEE; Use ieee.std_logic_1164.all;

entity a is port (in11 : in std_logic ); end a;

architecture a of a is
signal inBit    : Bit;
component b_1 port ( in1 : in bit); end component;

begin 
inBit <= to_bit(in11);
inst : b_1 port map ( in1=> inBit); end a;

There are restrictions that apply to actuals in port maps, c.f. vhdlref:

The actual, if a port or signal, must be denoted by a static name (see 6.1). The actual, if an expression, must be a globally static expression (see 7.4).

The thing is, both cases should be globally static...

BennyBarns
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  • If I write a wrapper function to "to_bit" in a package and then if I use that function, then it works. `code Package: package mgc_package is function mgc_to_Bit(p: std_ulogic) return bit; end package; package body mgc_package is function mgc_to_Bit(p: std_ulogic) return bit is begin return to_bit(p); end; end package body; VHDL Case: library work; use work.mgc_package.all; architecture a of a is .... begin inst : b port map ( in11=> mgc_to_Bit(in1)); end a; ` If I am able to use a function on actual in a portmap, then why can't I use "to_bit" function itself? – Dharmendra Oct 05 '12 at 09:37
  • to_bit is defined in the standard package, so in fact it is the same situation... no idea why that should work – BennyBarns Oct 05 '12 at 09:40
  • The Christian U. answer demonstrates why a conversion function would work. See 4.3.3.2 Association lists, *conversion function* (6.5.7.1 in -2008), the issue is the number of parameters which is overcome in -2008 (6.5.6.3 Port clauses) by associating an implicitly declared signal with the formal and the target of a concurrent assignment of the value of the expression (e.g. a function call with a globally static subtype for a return type mark). –  Apr 20 '17 at 20:58
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VHDL-93 allows type conversions and conversion functions in association lists. A conversion function is a special case of a function with only one argument.

Let's look at the declaration of to_bit:

function to_bit(s : std_ulogic; xmap : bit := '0') return bit;

Although to_bit(s) looks like a valid conversion function, it's not, because the declaration contains two arguments. The second argument xmap is used as the result when is_x(s) is true.

This is not a ModelSim bug, but maybe the error message is a bit cryptic. ModelSim figures that to_bit is meant to be a conversion function, but refuses to use it, because it has a second argument, and is thus not a valid conversion function.

A simple wrapper function can solve the problem:

function to_bit(s : std_ulogic) return bit is
begin
        return to_bit(s, '0');
end;

Note that the function can also have the name to_bit, because VHDL supports function overloading. It would be nice to have this in the package std_logic_1164.

Christian U.
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  • The xmap parameter supports modeling different logic rail systems. See IEEE Std 1076-2008 6.5.6.3 Port clauses, which provides for the use of non-static expressions (e.g. function calls with multiple parameter) for mode **in** formals using an implicitly declared signal, the target of an assignment of the expression being associated with the actual (as you do explicitly). While finding synthesis support might be problematic, your issue has been subsumed. It's generally not a -2002 to -2008 tool implementation high priority. –  Apr 20 '17 at 20:31