Implementing jump register control to single-cycle MIPS

Question

I am trying to implement jr (jump register) instruction support to a single-cycle MIPS processor. In the following image, I've drawn a simple mux that allows selecting between the normal chain PC or the instruction (jr) address.

MUX

How can I know that the instruction is JR to set the mux selection to '1'? I've already done jump and jump_and_link (although the image doesn't show it, as I don't have my project in hands right now), and to control them, I just check if the OP code is 10 (jump) or 11 (jal) in the main control and then set the mux sel to '1'. But I think I can't do the same with jr, as the instruction layout is distinct.

Don't know how much this will help you but: `jr $ra` jumps to the location last saved in the return address register. — wazy, Jun 22 '13 at 01:40
Yes, and I'm fetching the "saved location" from instruction register. But the problem is how to control when to set PC to this last location or default pc+4.. — user2509740, Jun 22 '13 at 04:09

score 6 · Accepted Answer · answered Jun 22 '13 at 23:52

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The opcode of a JR instruction has Instruction[31:26] == 0 (special) and Instruction[5:0] == 0x08 (JR). You need to look at both of these bit positions to decide that this is a JR instruction. The Control block on your diagram needs to have an additional input of Instruction[5:0]. The rs field in Instruction[25:21] selects the source register for this instruction. The PC needs to be assigned to rs when a JR instruction is executed.

answered Jun 22 '13 at 23:52

markgz

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Thank you @markgz, that was exactly what I was looking for. But how can I check if Instruction[5:0] is 0x08? – user2509740 Jun 23 '13 at 00:05
Something like this: (Inst[3] AND !Inst[2] AND !Inst[1] AND !Inst[0]) ? – user2509740 Jun 23 '13 at 00:41
Try `!Inst[5] & !Inst[4] & Inst[3] & !Inst[2] & !Inst[1] & !Inst[0].` You must check all of the bits of `Instruction[5:0].` – markgz Jun 23 '13 at 00:51

score 0 · Answer 2 · answered Oct 07 '16 at 07:28

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I think you can improve the performance of the hardware by implementing the JR mux before the Jump mux, since the JR mux is not dependent on the pcnext of the output of the Jump sel mux.

answered Oct 07 '16 at 07:28

Shankhadeep Mukerji

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Implementing jump register control to single-cycle MIPS

2 Answers2