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I am writing a simple MIPS architecture (supports only R-type and lw/sw instructions) in VHDL.

I am currently clocking each of the pipeline register on the rising edge. However, I had trouble deciding whether to clock register file, data memory and program counter on the rising edge or the falling edge.

After looking up online, it's pretty unanimous that you write to a register file on the falling edge. However, it's not so unanimous when it comes to data memory: some say to trigger the write to data memory on rising edge and some say falling edge, so I am a little bit confused here and need some explanation.

Oh, I also mentioned program counter because 1 website said to used falling edge; that kind of confused too as to why PC has to be clocked at the falling edge. That 1 website is this if anyone is interested: https://ls12-www.cs.tu-dortmund.de/daes/en/lehre/downloads/ravi/documentation/pipeline.html

Thanks very much.

Demi
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  • What is the target technology; FPGA or ASIC? Using the same clock for the entire design makes general design and timing analysis (STA) much easier, so there should be a good reason for using both rising and falling edge. Do you have a good reason, or is the idea solely based on some examples of register files using falling edge? – Morten Zilmer Mar 05 '14 at 12:20
  • Target technology is FPGA. The reason I am convinced to use falling edge for register files is quoted here: "the register file write in one cycle occurs before the register file read in the same cycle. This can be accomplished by writing to the register file on the falling edge (instead of the rising edge) of each clock cycle. A register file read from the same register will then have its value clocked into the ID/EX pipeline register at the next rising edge, ensuring that the just-written value is passed to the EX stage." – Demi Mar 05 '14 at 18:02

1 Answers1

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Read request of value written in same cycle occurs in all kind of designs, and is usually handled with bypass logic, whereby the written value is forwarded directly to the read output, without going through the registers. Such bypass is done in a single clock design.

Whether design with both rising and falling edge is to prefer (faster/better) in an FPGA, depends on the specific timing of the control signals and clocks. However, in FPGA all flip-flops are usually rising edge type, so the falling edge is made through a separate clock network that provides the inverted clock. The worst case skew calculated in Static Timing Analysis (STA) between these two clock networks may be so large, that there is no timing advantage in the introduction of a falling edge clock instead of just doing the bypass the usual way.

For implementation in an ASIC, there may be an advantage in a dual edge design, for example if the clock networks can be implemented with small skew, or if falling edge flip-flops are available in the target technology.

Morten Zilmer
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  • Thanks for the answer! Maybe another reason I don't want register file and RAM to be rising edge is because I already have 5 pipeline stages that trigger on the rising edge. If register file and RAM were to trigger at rising edge, I would essentially have 7 pipeline stages. I want to keep it at 5 stages, that's why I think I should trigger write to reg/RAM on falling edge. By the way, I should mention that the register file I am implementing has asynchronous read as oppose to the register file you posted here: http://stackoverflow.com/questions/19942067/writing-a-register-file-in-vhdl?rq=1 – Demi Mar 05 '14 at 22:59
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    An alternative to using both rising and falling edge, is to design with multi-cycle path on a double-frequency clock, which may give better timing. – Morten Zilmer Mar 06 '14 at 05:02