VHDL assigning literals

Question

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me trying to assign literal values to these types defined as:

variable LCD_DATA: unsigned(19 downto 0) := 0;

But in my IDE (Quartus), I get a complaint "UNSIGNED type does not match integer literal." I also get complaints for adding numbers to types defined like this. Whats the preferred change I need to make?

fru1tbat · Accepted Answer · 2014-03-18T23:06:07.227

6

See other answers, and note that for non-zero literals, you probably want to do something like:

variable LCD_DATA: unsigned(19 downto 0) := to_unsigned(n, 20);

Substitute a literal for n. This works for n=0 too, of course, but it's not as tidy as (others => '0').

edited Mar 18 '14 at 23:06

answered Mar 18 '14 at 11:53

fru1tbat

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LCD_DATA'LENGTH isn't available until after the semicolon. IEEE Std 1076-1993 10.3 Notes "2—The rules defining immediate scope, hiding, and visibility imply that a reference to an identifier, character literal, or operator symbol within its own declaration is illegal (except for design units). The identifier, character literal, or operator symbol hides outer homographs within its immediate scope—that is, from the start of the declaration. On the other hand, the identifier, character literal, or operator symbol is visible only after the end of the declaration (again, except for design units)." – Mar 18 '14 at 23:02
For -2008 that's Section 12.3 Visibility, same Note 2. – Mar 18 '14 at 23:16
The original erroneous answer provided `variable LCD_DATA: unsigned(19 downto 0) := to_unsigned(n, LCD_DATA'length);` Essentially something isn't available until it is declared and the declaration is `variable_declaration ::= [ shared ] variable identifier_list : subtype_indication [ := expression ] ;`, which is where the after the semicolon comment comes from. See IEEE Std 1076-1993 4.3.1.3 (6.4.2.4 -2008) Variable declarations. – Mar 18 '14 at 23:26
Yeah, I'm so used to using that construct in processes, etc., I forgot it was illegal in declarations. – fru1tbat Mar 19 '14 at 13:53

score 1 · Answer 2 · 2014-03-18T07:04:40.093

unsigned is related to std_ulogic, where the value for an element would be '0'.

variable LCD_DATA: unsigned (19 downto 0) := (others => '0');

which provides an aggregate for the default assignment with all elements set to '0'.

You can't assign a single element of integer type to an array of std_ulogic elements.

You can add signed or unsigned to a natural (unsigned) or integer (signed) using "+" functions defined in package numeric_std:

  -- Id: A.5
  function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
  -- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
  -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.

  -- Id: A.6
  function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
  -- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
  -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.

  -- Id: A.7
  function "+" (L: INTEGER; R: SIGNED) return SIGNED;
  -- Result subtype: SIGNED(R'LENGTH-1 downto 0).
  -- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
  --         vector, R.

  -- Id: A.8
  function "+" (L: SIGNED; R: INTEGER) return SIGNED;
  -- Result subtype: SIGNED(L'LENGTH-1 downto 0).
  -- Result: Adds a SIGNED vector, L, to an INTEGER, R.

score 1 · Answer 3 · answered Mar 18 '14 at 06:54

--Either 
variable LCD_DATA: unsigned(19 downto 0) := (others => '0');
--Or you can also write it like 
variable LCD_DATA: unsigned(19 downto 0) := "00000000000000000000";

And for the 2nd part of your question while adding number of this type.

library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;

Check whether you have used above libraries in the code or not.

VHDL assigning literals

3 Answers3