Verilog blocking and non-blocking in a sequence

Question

I have the following in Verilog:

reg a;

always @ (clk)
begin
  a = 0;
  a <= 1;
  $display(a);
end

What value of literal 'a' would show me? Is that 0 or 1?

possible duplicate of [How to interpret blocking vs non blocking assignments in Verilog?](http://stackoverflow.com/questions/4653284/how-to-interpret-blocking-vs-non-blocking-assignments-in-verilog) — Qiu, May 11 '14 at 11:36
@Qiu, this is not duplicate of that. It is close to that, but I want to see others' answers. --- I know the following about scheduling semantics in Verilog simulators: the order in which events are scheduled to execute is as below: 1- active events such as blocking assignment and RHS calculation of non-blocking assignments. 2- Inactive assignments, and 3- Nonblocking assign update. For the above example, I believe $display may show 0 or 1, depending on when display gets executed. — Mehdi, May 12 '14 at 05:29
@Ari, can you recommend a good simulator in Mac that is free for use so I can simulate this? — Mehdi, May 12 '14 at 05:34
There's a simple answer to your (good) question, but you've posted code that has obviously never been near a simulator. If you fixed it first, you'd be more likely to get an answer. — EML, May 12 '14 at 08:46
seems like you know the answer to your question ..If you know about scheduling events this question should be fairly straight forward — chitranna, May 12 '14 at 11:33
@TrafalgarLaw: The question seems to be about when the argument to `$display` is evaluated — Moberg, May 12 '14 at 11:53
@Mehdi: I don't know a simulator on mac, but you can use this free online simulator: http://www.edaplayground.com/ which is based on Modelsim — Ari, May 13 '14 at 10:59

score 3 · Accepted Answer · edited May 12 '14 at 16:30

Verilog simulation occurs in 5 queues as stated in IEEE 1364-1995 § 5.3, IEEE 1364-2001 § 5.3, and IEEE 1364-2005 § 11.3:

Active Event (before #0)
- Evaluate RHS of all non-blocking assignment
- Evaluate RHS and change LHS of all blocking assignments
- Evaluate RHS and change LHS of all continuous assignments
- Evaluate inputs and change outputs of all primitives
- Evaluate and print output from $display and $write
Inactive Event (after #0)
- Evaluate RHS after #0 delay, otherwize same processes as Active Event
- Callback procedures scheduled with PLI routines such as tf_synchronize()(deprecated in IEEE 1364-2005) and vpi_register_cb(cbReadWriteSynch)
NBA Update
- Change LHS of all non-blocking assignments
Monitor Event
- Evaluate and print output from $monitor and $strobe
- Call PLI with reason_rosynchronize(deprecated in IEEE 1364-2005)
Future
- Events to occur at some future simulation time

Since $display occurs before the non-blocking assignment is assigned , the value will be 0. Note the order of execution may change in each queue.

Verilog blocking and non-blocking in a sequence

1 Answers1