Get internal signals of vhdl design in ncvhdl (alternative to modelsim's signal spy)

Question

In ModelSim you can use something like

in modelsim we can use init_signal_spy("../.../sig", mysignal);

to get deep hierarchy signals. Is there a way to get such signals with Cadence's NCVhdl?

This should be flagged "SimVision", which is the name the tool, but that flag does not seem to exist.

score 7 · Accepted Answer · answered Jul 02 '14 at 16:24

7

If Cadence tools support VHDL-2008, you can access signals, shared variables, or constants in other levels of your design via external names.

Direct usage is as follows.

A <= <<signal .tb_top.u_comp1.my_sig : std_logic_vector >>;

Note that the object must be elaborated before the reference. Since VHDL designs are elaborated in order of instantiation later designs may reference into earlier ones.

Use an alias to create a local short hand name:

alias u1_my_sig is <<signal u1.my_sig : std_logic_vector >>;

Path starts with:

“.” = path starts at top level: “.tb_top.my_sig”
“u1” = path starts from current level: “u1.my_sig”
“^” = path starts from level above current: “^u2.my_sig”

answered Jul 02 '14 at 16:24

Jim Lewis

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but then the whole file must be compiled as VHDL 2008, which is not always possible – Sadık Jul 03 '14 at 08:36
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If the file compiles in VHDL-93, then it should compile in VHDL-2008. If your simulator does not support VHDL-2008 external names, then file a bug report. This is the only way vendors prioritize these things. – Jim Lewis Jul 03 '14 at 18:20
When compiling my testbench first without **-V93** I got the error message ": This feature is allowed only in 93[13.7]". I guess it takes 87 as default. But with **-V200X** everything worked. So your solution should work for me. – Sadık Jul 04 '14 at 08:46

score 0 · Answer 2 · edited May 23 '17 at 12:06

As one can see here, the function is called nc_mirror.

 nc_mirror (destination => "destination",

           source => "source",

           verbose => "verbose");

It takes a destination and a source and does just the same as init_signal_spy does for modelsim. The third parameter is optional. Additionally it supports mirroring arrays or records.

In this interesting answer a wrapper package is provided that converts the nc_mirror or init_spy_signal (and others) to a function "probe".

Get internal signals of vhdl design in ncvhdl (alternative to modelsim's signal spy)

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