Array of systemverilog interfaces with different inputs

Question

I would like to instantiate an array of systemverilog interfaces where each array element uses a different input.

If all the elements use the same input, then the instantiation is simple:

x_if x_IF[`NUM_INTERFACES](clk);

Here, if `NUM_INTERFACES is 2, then the clk input goes to both x_IF[0] and x_IF[1].

But if I also have

reg clk[`NUM_INTERFACES];

how do I instantiate x_IF so that clk[0] is input to x_IF[0] and clk[1] is input to x_IF[1]?

This is a simple example; I am looking forward to implement this in some sort of loop (probably using generate) for an array of 12 interfaces.

If you implement it using a `generate` loop, you won't have an array, but 12 different instances each in its own scope. — Tudor Timi, Dec 01 '14 at 18:52
Exactly, that's why I was wondering how to get this done in a loop. Finally got a solution; I left the interface inputs unconnected in the declaration and later assigned values to them in the generate loop. — Kaushal Modi, Dec 01 '14 at 20:37

score 3 · Accepted Answer · edited Dec 02 '14 at 01:25

3

I would avoid using assign statements, especially with hierarchical references; it makes the code much more difficult to read and maintain.

You could have just done

reg clk[`NUM_INTERFACES];
x_if x_IF[`NUM_INTERFACES](clk);

A feature with arrays of instances is that if the width of a signal being connected to a port is a multiple of the port width, then each instance sill get a slice of the the signal.

See LRM 1800-2012 section 28.3.6 Primitive instance connection list that applies to module ports as well.

If you use a generate loop instead of an array of instances, then I would do

reg  clk[`NUM_INTERFACES];

generate
   for (genvar i=0; i<`NUM_INTERFACES; i++) begin :loop
      x_if x_IF(clk[i]);
   end
endgenerate

edited Dec 02 '14 at 01:25

Greg

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answered Dec 01 '14 at 22:09

dave_59

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Did you mean `x_if x_IF[i](clk[i]);`? Even then, wouldn't that create multiple interface arrays of incremental lengths up to NUM_INTERFACES? Or does it work because of `(clk[i])`? – Kaushal Modi Dec 02 '14 at 00:42
No I did not mean that. Each iteration of the `generate` for-loop will create one instance named `loop[i].x_IF` because the begin block named `loop` will get elaborated into loop[0], loop[1], etc. – dave_59 Dec 03 '14 at 18:15
Thanks for the explanation. I was unaware of the ability to reference signals using `loop[i]`. – Kaushal Modi Dec 03 '14 at 18:42
Note that you can only reference loop[i] if i is a genvar or constant. – dave_59 Dec 04 '14 at 04:38

score 0 · Answer 2 · answered Dec 01 '14 at 20:36

I was able to implement this by assigning the interface inputs from inside the generate loop and leaving them unassigned in the declaration.

x_if x_IF[`NUM_INTERFACES]();
reg  clk[`NUM_INTERFACES];

// Code to create clk[`NUM_INTERFACES]

generate
   for (genvar i=0; i<`NUM_INTERFACES; i++) begin
      // Assume that the input port of x_if is called `inp`
      assign x_IF[i].inp = clk[i];
   end
endgenerate

Array of systemverilog interfaces with different inputs

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