I'm trying to learn about SystemVerilog. While reading about it, I came across the following code, which I cannot fully understand:
Test1.
class A ; 
  task disp();
    $display(" This is class A "); 
  endtask 
endclass 
class EA extends A ; 
  task disp (); 
    $display(" This is Extended class A "); 
  endtask 
endclass 
program main ; 
  EA my_ea; 
  A my_a; 
  initial 
  begin 
    my_a.disp(); 
    my_a = my_ea; 
    my_a.disp(); 
  end 
endprogram 
Test2.
class A ; 
  virtual task disp (); 
    $display(" This is class A "); 
  endtask 
endclass 
 
class EA extends A ; 
  task disp (); 
    $display(" This is Extended class A "); 
  endtask 
endclass 
program main ; 
  EA my_ea; 
  A my_a; 
  initial 
  begin 
    my_a = new(); 
    my_a.disp(); 
    my_ea = new(); 
    my_a = my_ea; 
    my_a.disp(); 
  end 
endprogram 
I have some questions about the test1 code above. There is a call to some 'new' function, but the implementation of that is not provided anywhere. How can this code compile and run then?
Also in the test2, you can see the 'virtual' keyword. I do not understand the reason behind using 'virtual'. Can you please explain why do we have to use 'virtual' in this context?
update
I'd like to implement the example code from Greg. But I've got some problem as the below
                         Chronologic VCS (TM)
         Version J-2014.12-SP1-1 -- Wed Aug  8 08:33:23 2018
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Parsing design file 'design.sv'
Parsing design file 'testbench.sv'
Error-[SE] Syntax error
  Following verilog source has syntax error :
  "testbench.sv", 21: token is '('
    function(A a);
             ^
1 error
CPU time: .073 seconds to compile
Exit code expected: 0, received: 1
Done
 
     
    