Pass parameters in Verilog

Question

I am writing a module in Verilog that uses parameters. Later I will need to implement it several times in my project using different parameters, so instead of crating several modules I want to pass the parameters as if they were inputs, although they are specified in the compilation.

I think this can be done in VHDL, so I guess it can be done in Verilog too although I cannot find anything.

Possible duplicate of [Passing parameters to Verilog modules](http://stackoverflow.com/questions/27555273/passing-parameters-to-verilog-modules) — wilcroft, Feb 22 '16 at 17:07

score 0 · Accepted Answer · answered Feb 22 '16 at 18:39

Module parameters can be overridden in these 2 ways:

Using defparam statement:

module Stack;

parameter param1 =  1;
parameter param2 = 12;

endmodule

module Test;

defparam s1.param1 =  6;
defparam s1.param2 = 32;

Stack s1();

endmodule

Passing parameters during instantiating: in this method, parameters must be overridden in the order they were defined so code below, is the same as above.
```
module Stack;

parameter param1 =  1;
parameter param2 = 12;

endmodule

module Test;

Stack #(6, 32) s1();

endmodule
```
- In Verilog 2001, there is a new feature which makes it more readable (note that above codes all work in Verilog 2001).
```
module Stack;

parameter param1 =  1;
parameter param2 = 12;

endmodule

module Test;

Stack #(.param1(6), .param2(32)) s1();

endmodule
```

score 0 · Answer 2 · answered Feb 25 '16 at 07:32

Another way.

`module top #(
parameter N, // Number of instance
parameter [(N*32-1):0] A, // First Parameter
parameter [(N*2-1):0] B   // second parameter
);
generate
for (int i=0; i<N; i++) begin: instance
  s #(.A(A[(i*32-1):0]),
      .B(B[(i*2-1):0])
     ) s_i;
end
endgenerate`

score -1 · Answer 3 · answered Feb 25 '16 at 06:27

You can directly assign parameter during the input and output assignment. for example: " parameter i0=0,i1=1; " and call these values in code such as:" a[0]=N[i0];" =>the 0th bit of input N; will be stored in 0th bit of reg a; "a[1]=N[i1];"=> the 1th bit of input N; will be stored in 1th bit of reg a; if your N is 4'b1011, then the value of " a=0011 ". You may have to initialize a to 0.

Pass parameters in Verilog

3 Answers3