Memory code errors in Verilog

Question

I write Verilog program to simulate memory transfer to Temp , but i got a lot of errors, help please.

wire    [64:0] temp,mem [0:256];
wire [15:0]       w0, w1, w2, w3;
wire    [7:0]       block_nr;
integer i ;



for ( i=0; i <3; i = i + 1) begin
   temp = mem [i];
   data_mem [i] = {block_nr, w0,w1, w2, w3 };
   block_nr = block_nr +1;


end

This error for Temp=mem [i} Procedural assignment to a non-register temp is not permitted, left-hand side should be reg/integer/time/genva, — Hayder Al-Amily, Mar 24 '16 at 21:03
In order to store/hold some data, `reg` must be used. Any assignments must be done in procedural blocks. Refer (http://stackoverflow.com/questions/5360508/using-wire-or-reg-with-input-or-output-in-verilog) for information about reg and wire usage. — sharvil111, Mar 25 '16 at 01:06

score 0 · Answer 1 · answered Mar 25 '16 at 08:58

5There are many errors in your code. Here are some:

a) Instead of this:

wire    [64:0] temp,mem [0:256];

perhaps you mean this?

wire    [64:0] mem [0:256]; // this might be a reg, too, one cannot tell from your code snippet
reg     [64:0] temp;

i) I don't think you meant temp to be a 65x257 array as well as mem? And did you mean "64"? Or "63"? Or (see below) "71"? And did you mean "256"? Or "255"?

ii) You cannot assign to a wire from inside a procedural block.

b) This needs to be a reg, too, because (again) you cannot assign to a wire from inside a procedural block.

reg    [7:0]       block_nr;

c) This code needs to go inside a procedural block, either initial or always. Which depends on your design intent - I cannot tell this from your snippet of code. Let's assume initial:

initial begin
 for ( i=0; i <3; i = i + 1) begin
     temp = mem [i];
     data_mem [i] = {block_nr, w0,w1, w2, w3 };  // what is "data_mem"? Did you mean "mem"?
                                                 // if you did mean "mem", did you notice that "{block_nr, w0,w1, w2, w3 }" is 72 bits wide?
     block_nr = block_nr +1;
  end
end

If this is intended to be synthesised, the you cannot use initial. If you do intend to synthesise this, you are a long way from a working solution.

I must emphasise, however, that these are merely suggestions. It is not possible to completely correct errors in code whose design intent is not known.

Memory code errors in Verilog

1 Answers1