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What happens behind the scenes when adding to memory from a register?

For example:

.data 
foo dword 1

.code
mov eax, 10
add foo, eax

Does it move the contents of foo to some register, do the addition in the ALU and returns it to memory?

shinzou
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    Conceptually, you can definitely think about the instruction this way. Whether an actual physical processor loads the value from memory into some (unnamed/non-architectural) register before (and/or after) the ALU-operation is another question. – EOF Apr 03 '16 at 20:38
  • So in a sense this takes more clock cycles than addition between registers? @EOF – shinzou Apr 03 '16 at 21:18
  • It's a non-atomic `read-modify-write`-operation on a memory operand, so it will take read-latency (best-case ~3 cycles from L1 d$, bad case ~300 cycles (RAM access), worst case > a million cycles (memory was paged to disk)), the ALU latency (1 cycle), then a write (buffered, likely to hit cache after the read). So, yes, it takes a bit longer than `add register, register`. – EOF Apr 03 '16 at 21:24
  • If you want to count cycles, go read [Agner Fog's guides, esp. the microarchitecture pdf](http://www.agner.org/optimize/) so you can understand his instruction tables (of latency/throughput/uops + ports. Also other links from the [x86 tag wiki](http://stackoverflow.com/tags/x86/info). Re: your question, technically the load probably doesn't have a physical register as a destination. When the load uop's result is ready, I think it's forwarded right to the ALU the `add` uop is scheduled for. That result is then forwarded to the store-data uop. (all these uops are decoded from the `add` insn) – Peter Cordes Apr 04 '16 at 00:30

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