Verilog: Assigning a register to a register

Question

In the below Verilog assignment register rotationDoneR is assigned to the Signal and then the other register rotationDoneRR is assigned to the same register. Doesn't that mean that both registers hold the same value and the condition is never true?

input wire RotationDone; // from the module definition

reg rotationDoneR;
reg rotationDoneRR;

rotationDoneR <= RotationDone; 
rotationDoneRR <= rotationDoneR;  

if ( rotationDoneR && (! rotationDoneRR ) ) begin 
    InterruptToCPU <= 1; 
end

Thanks for any clarification!

score 4 · Answer 1 · edited May 23 '17 at 11:59

I assume there is some procedural block based on the edge of clocking event in your code.

When you have non blocking assignments (<=), the evaluation of RHS takes place in Active Event Region, while the LHS is updated in the NBA region.

Consider the following example, the non-blocking assignments evaluates RHS in Active region and stores the value internally, temporarily for the same time stamp (the older value of a is stored internally here). Then in the NBA region, the LHS are updated (b gets the older value of a and a gets the value of inp).

// synthesize to simple wire
a = inp;
b = a;

// synthesize to shift register
a <= inp;
b <= a;

Similarly, here rotationDoneRR is the flop-ed version of rotationDoneR. Since, on some clock edge, rotationDoneR is loaded with RotationDone and at the same time, rotationDoneRR is loaded with rotationDoneR.

So, the if condition evaluates true whenever: The current input value is TRUE (current input RotationDone = 1'b1) and negated previous value of input (previous input RotationDone = 1'b0) is satisfied.

Refer to non-blocking assignments link and many other PDFs over the net, including CummingsSNUG2000SJ_NBA_rev1_2 Paper for more information.

Verilog: Assigning a register to a register

1 Answers1