Distinguish and expand text macro nested in define macro

Question

I would like to define a parameter MYTYPE using text macro, whose value is passed over by text macro, eg

`define MY_FEATURE(nam,def) parameter nam=def;

and then

`MY_FEATURE(MYTYPE, 1)

But the value is mixed by those who are defined by other text macros, eg

`MY_FEATURE(NEWTYPE, 2)
`MY_FEATURE(MYTYPE, NEWTYPE)

The latter case will not work unless the def in define MY_FEATURE is added with the directive dot.

I need to distinguish this two different cases and automatically expand the macro - only if it is defined, so I came up with this code but I got error.

`define yea 1
`define nop 0
`define MY_FEATURE(nam,def) `ifdef def parameter nam=`def; `else parameter nam=2; `endif

module test;

  `MY_FEATURE(MYTYPE,yea)
  initial begin
    $display("%d",MYTYPE);
  end
endmodule

The above code works and gives a 1 as output. However if I write

`MY_FEATURE(MYTYPE,10)

since for other cases I need to assign an actual number to the parameter, then I will get

 `ifdef without a macro name - ignored.

My desired result is MYTYPE is assigned as 10. Is there any way to achieve this? Thanks.

Code can be found here http://www.edaplayground.com/x/6Jha

score 1 · Accepted Answer · edited May 23 '17 at 12:25

I think you are overthinking it. `define creates an directive expression. When when you pass a directive as parameter to another directive you can pass it as `yea.

Here is an example:

`define yea 1
`define nop 0
`define MY_FEATURE(nam,def) parameter nam=def;

module test;
  `MY_FEATURE(MYTYPE,`yea)
  `MY_FEATURE(MYTYPE2,10)
  `MY_FEATURE(MYTYPE3,MYTYPE+MYTYPE2)
  initial begin
    $display("%d %d %d",MYTYPE, MYTYPE2, MYTYPE3); // displays: 1 10 11
  end
endmodule

http://www.edaplayground.com/x/5Pgf

Verilog-AMS (superset of Verilog-A) is a language of its own, derived from Verilog (IEEE Std 1364); according the manual. This means your MY_FEATURE never creates new directives; it creates parameters. Directives and parameters are both treated as constants in simulation but act differently in compile. The `define/parameters relation in Verilog (and Verilog derived languages) is equivalent to C's #define/const relation. Unlike C, to access the value of a `define requires a ` prefix.

Neither directives or parameters cannot start with a numeric value. The first character must be an alpha or underscore (aka [a-zA-Z_]). There for 10 can never be a directives and even trying to use it is illegal syntax. There is noway for the compile to recover from an illegal syntax directive name. This is way I suggested passing `yea instead of yea.

If someone build you a nice model, then it should come with equally nice documentation or some way of getting support.

Thank you. It works in system verilog but i'm actually using verilog a. they build a pretty large (and nice) model of a real device and use lots of directive statements to define constants. i believe they have used hspice but i can only use virtuoso / spectre and they don't seem to like this setting. — Yvon, May 04 '16 at 21:33
I'll append my comment to my answer as it is a bit long and code formatted \` in comments do not format well — Greg, May 05 '16 at 23:07
Thank you, Greg. Now i understand there is little way i could get around this. i believe they are nice people making things accepted by the industry, but i don't see any documentation on the code itself besides the one on the physical model they create. i as a beginner am using my common sense in verilog/vhdl coding. Just replaced a few hundreds of statements that refer to other parameters - at least it works! — Yvon, May 07 '16 at 01:28

Distinguish and expand text macro nested in define macro

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