Below is the code of VHDL which uses IF block. In the last "elsif", the value of "my_choice" is assigned to "ch4". Then "else" block is executed, since no condition is satisfied. But, is there any chance that "my_choice" gets some other value other than (ch1,ch2,ch3,ch4), like high impedence (or anything else)? If so, how can i avoid that? Since this assignment can change the operation of the code.
    entity entity_name
    port
        .....
        .....
    end entity_name;
    architecture bhvr of entity_name
    type choices is (ch1, ch2, ch3, ch4);
    signal my_choice,next_choice : choices;
    begin
        process(clk, reset)
        begin
            if reset='1' tehn
                --------reset
            else
                  my_choice<=next_choice;
            end if;
        end process;
        process(my_choice)
        begin
            if my_choice = ch1 then
                next_choice <= ch2;
            elsif my_choice = ch2 then 
                next_choice <= ch3;
            elsif my_choice = ch3 then
                next_choice <= ch4;
            else  ------------------------------------coming to ch4
                ---- task for ch4
        end process;            
    end architecture;