Query for VHDL synthesis for IC Design (Not FPGA), specifically in case of variable assignment

Question

If for a given process, I declare a variable (let's say a 1 bit variable, variable temp : std_logic;) then can I assign a value to the variable if a given condition returns true, i.e.

if (xyz=1) then --Assuming that this condition returns TRUE
temp:= '1';

?? Will this logic be synthesizable for ASICs?

Matthew Taylor · Accepted Answer · 2017-04-23T11:06:24.250

Yes. Variables are synthesisable for both FPGA and IC. A process is a little bit of software that models a little bit of hardware. That little bit of software can use variables, but as variables are only in scope within a process, ultimately you do have to drive a signal - the output of the little bit of hardware.

For example, here is some combinational logic:

process (A, B, C, D)
  variable TMP : std_logic;
begin
  if A = '1' then
    TMP := B and C;
    TMP := TMP and D;
  else
    TMP := '0';
  end if;
  F <= TMP;
end process;

Here is an example of using a variable that will synthesise to combinational logic on the D input of a flip-flop (because it is in a clocked process):

process (CLOCK)
  variable TMP : std_logic;
begin
  if rising_edge(CLOCK) then
    TMP := A and B;
    Q <= TMP;
  end if;
end process;

And here is an example of using a variable in a clocked process that will synthesise to a flip-flop (with an AND gate on its D input):

process (CLOCK)
  variable TMP : std_logic;
begin
  if rising_edge(CLOCK) then
    Q <= TMP;
    TMP := A and B;
  end if;
end process;

The only difference between the two clocked processes is the order. In the first, the variable is assigned to before being accessed; in the second, it is accessed before it is assigned to.

If you assign to a variable before accessing it in a clocked process combinational logic will be inferred;
if you access a variable before assigning to it in a clocked process, a flip-flop will be inferred.
Do not ever access a variable before assigning to it in a combinational process: latches will be inferred.

Variables retain their value between executions of a process. Therefore, if a variable is accessed before being assigned to in a clocked process, the value read must have been written on a previous execution of the process. In a clocked process, that previous execution will have been on a previous clock edge: hence, a flip-flop is inferred.

So, I can't really assign boolean values to the variables?? Will I have to assign signals and drive it from an input pin on IC?? — Gaurav Singh, Apr 23 '17 at 03:28
I don't understand your question. `boolean` is a _type_. You can have `boolean` signals or variables. Both would be synthesisable. But it is better to use the _type_ `std_logic` than `boolean`, because the type `boolean` cannot represent unknown/uninitialised/don't care. I've edited to question to try to make it clearer. — Matthew Taylor, Apr 23 '17 at 07:43
I think I didn't phrased my question correctly. What I meant is - if I have to assign a value say `'0'` to the variable `temp` as defined in the question above, Do i need to drive this `'0'` value from a pin on IC (mapped as an input port) via a signal and then assign it to variable, or say in any process for a given condition, if the condition is true then assign this value to the variable `temp` i.e. , `temp<='0';` So can I directly assign a constant value to any variable and hope that It will synthesize ?? — Gaurav Singh, Apr 23 '17 at 09:55
I've edited the first example again. It is synthesisable. Constants are synthesisable. Does that answer your question? — Matthew Taylor, Apr 23 '17 at 11:07

Query for VHDL synthesis for IC Design (Not FPGA), specifically in case of variable assignment

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