How to Initialize a Register of Vectors?

Question

I have defined a register of vectors like this

val my_reg = Reg(Vec(n, Bits(32.W)))

and I access the elements of this register in a for loop using my_reg(i).

Now, I like to initialize this register to zero, so I change the variable definition to this

val my_reg = Reg(Vec(n, Bits(32.W)), init = UInt(0))

However, I get the following compilation error when I want to access the elements of this register

chisel3.core.Data does not take parameters
my_reg(i) := io.a(i)

How can I define a register of vectors and properly initialize them synchronously?

Chick Markley · Accepted Answer · 2017-04-27T19:27:56.647

7

Use RegInit instead. I believe the following statement will do what you want

    val my_reg = RegInit(Vec(Seq.fill(n)(0.U(32.W))))

The Vector is initialized by a Seq of UInt zeros that are 32 bits wide

edited Apr 27 '17 at 19:27

answered Apr 27 '17 at 16:23

Chick Markley

Thanks a lot. You just need to add another right parenthesis at the end. – Matt Apr 27 '17 at 18:22
You may also want to remove "that are". It's written twice. I can't edit your solution. – Matt Apr 27 '17 at 18:36
I am new to Chisel and Scala -- it looks like Seq.fill is a Scala function that creates an "array" of elements -- however, I'm not familiar with "0.U(32.W)" syntax, could someone explain the mechanics of the syntax? (I get that it defines a UInt whose value is zero -- but the details of the syntax mechanics are foreign and I can't find where in the Scala or Chisel manual to look -- no real keywords to search for this) Thanks! – seanhalle May 02 '17 at 00:51
0.U(32.W) means the value zero as a unsigned hardware integer, that is 32bits wide. – Chick Markley May 02 '17 at 22:01
3

Change Vec to VecInit because of the following: `Warning:(235, 34) method do_apply in object Vec is deprecated (since chisel3): Vec(elts) is deprecated, use VecInit(elts) instead val loadEnableReg = RegInit(Vec(Seq.fill(config.LoadersNum)(0.U)))` – edc Sep 19 '18 at 21:56

score 5 · Answer 2 · answered Dec 17 '19 at 16:53

5

Looks like in Chisel 3 this should be VecInit instead of Vec:

val initRegOfVec = RegInit(VecInit(Seq.fill(4)(0.U(32.W))))

answered Dec 17 '19 at 16:53

Edward Halferty

2 Answers2