Verilog Code Error: Range must be bounded by constant expressions

Question

I have written a code for a 52 bit multiplier that I need to give out in standard form (IEEE 754 Floating point standard for 64 bit numbers). So afterwards I am checking, how many bits has it exceeded from 64, so that i would put that number into exponent.

module mul1(output reg [103:0] p, 
        output reg [51:0]  c, 
        input [51:0]   x,
        input [51:0]   y); 


reg [103:0]a;
integer i; 

always @(x , y)
begin 
  a=x;
  p=0; // needs to zeroed
  for(i=0;i<104;i=i+1)
  begin
    if(y[i])
      p=p+a; // must be a blocking assignment
    a=a<<1;
  end

  for(i=103;i>=0;i=i-1)
  begin
    if (p[i])
        c=p[i:i-51];
        break;
    end

  end
endmodule

it is giving an error: Range must be bounded by constant expressions for the line: c=p[i:i-51]; How can I solve this?

Possible duplicate of [Verilog: "... is not a constant"](http://stackoverflow.com/questions/29815974/verilog-is-not-a-constant) — Qiu, May 04 '17 at 05:46

score 1 · Accepted Answer · edited May 23 '17 at 12:10

You can't have a variable part/slice selection (variable width). Think of the assignment from the perspective of the variable c. c is 52 bits wide, so you need to assign it 52 bits of p. The loop just needs to select which 52 bits. That's what the variable part-select operator is for. There's a good explanation here: Indexing vectors and arrays with +:

It looks like:

c=p[i+:52]

Which means, select from p starting at (lower bit) i going up to i+52-1 and assign to c.

module mul1(output reg [103:0] p,
        output reg [51:0]  c,
        input [51:0]   x,
        input [51:0]   y);


reg [103:0]a;
integer i;

always @(x , y) begin
  a=x;
  p=0; // needs to zeroed
  for(i=0;i<104;i=i+1) begin
    if(y[i]) begin
      p=p+a; // must be a blocking assignment
    end
    a=a<<1;
  end

  for(i=103;i>=0;i=i-1) begin
    if (p[i]) begin
      c=p[i+:52];
      break;
    end
  end
end
endmodule

Also, you need a 'begin' after the 'if' in the 2nd loop and an 'end' to close the always block. The code above compiles for me.

Verilog Code Error: Range must be bounded by constant expressions

1 Answers1