Is it true or false in Verilog? I do not understand what does it mean by mixing..Does it changes the output directly if it works?
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3Possible duplicate of [this](https://stackoverflow.com/questions/4653284/how-to-interpret-blocking-vs-non-blocking-assignments-in-verilog) SO question. – Jeroen Heier May 23 '17 at 17:50
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It's not even synthesizable though it may work in simulation. – Laleh May 23 '17 at 18:45
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Yes I think it may be related to synthesizability only, not simulation – Karan Shah May 28 '17 at 06:28
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The rule needs to be clarified.
Do not assign the same variable using both blocking and non-blocking assignments within the same block. The problem usually manifests itself when describing an asynchronous reset.
always @(posedge clk or negedge rst)
if (!reset)
q = 0;
else
q < = d;
If the two events occur at the same time, but q<= d gets processed before the q=0, then there is a pending update to q after it gets set to 0, so that gets lost. There are a number of other scenarios.
dave_59
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Can you please be more clear? When the TWO events (I guess you are talking about posedge clk and negedge rst) occur at the same time, only q = 0 will get executed. q <= d will not. Why are you talking that q <= d might execuute and then q=0 might execute? – user3219492 Sep 12 '19 at 06:25
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Yes, those are the two events. `q<=d` might get executed because `rst` is still 1, the `negedge rst` has not happened yet. – dave_59 Sep 12 '19 at 07:17