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The Intel Software Development Manual says this about the neg instruction:

The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set according to the result.

I thought that AF and CF would be set as if neg %eax were replaced by,

not %eax   # bitwise negation
add $1, %eax

But that's not the case, negating 0x6ffffef5 on a real CPU sets AF and CF.

tbodt
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  • @EvanCarroll: Why did you change this question from AT&T to Intel syntax? Now my answer looks weird. – Peter Cordes Oct 26 '18 at 00:13
  • @PeterCordes I don't care to get into that holy war, bowing out (reverted back to GAS). Though I do think that would be a good thing to standardize on the [intel] or [x86] tag. – Evan Carroll Oct 26 '18 at 00:21
  • @EvanCarroll :The [Intel] tag has nothing much to do with Intel Assembly language syntax. It is the Intel architectures in general. There are [intel-syntax] and [att] tags for questions specific to Intel or AT&T assembly language syntax though. – Michael Petch Oct 26 '18 at 00:41
  • @MichaelPetch: The `[intel]` tag is for questions about any stuff Intel makes, like their math libraries, their graphics hardware / quicksync, computer-vision libraries, or whatever. (I follow the tag to find mis-tagged asm questions. A fair amount of `[intel]` questions aren't about asm.) Questions about x86 assembly language or the x86 ISA normally should only have the `[intel]` tag if it's specifically about Intel's implementation of that ISA, e.g. a performance or optimization question about Intel CPUs like Skylake or . The equivalent question for Ryzen would have an `[amd]` tag. – Peter Cordes Oct 26 '18 at 01:21
  • @PeterCordes Where did I suggest the [Intel] questions were about assembly questions? In fact quite I said quite the contrary. As for how people use the [intel] tag is a different matter, BUT the one line description says this _For issues related to Intel semiconductor chips and assemblies, Intel architectural features and ISA extensions, and Intel chips micro-architecture._ Which is why I said _Intel architectures in general_ . The crux of my comment is that [intel-syntax] and [att] tags are related to assembly language **syntaxes**. We have tags for those. – Michael Petch Oct 26 '18 at 01:27
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    @MichaelPetch: Ah I see. The tag phrasing sounds to me like it's limiting the scope to Intel-specific x86 extensions (like transactional memory), not to x86 ISA questions in general. (Which is how I read your comment. I also wasn't sure if you were were saying it was limited to that, or if that was just part of what it covered, sorry for being pedantic). Given that there are already `[x86]` and `[itanium]` tags for those subjects, I think that's appropriate. I think we agree that we want x86 questions tagged x86 for sure so they're findable, not scattered across `[intel]` and `[x86]`. – Peter Cordes Oct 26 '18 at 01:37
  • @PeterCordes : As for your final sentence, yes we are very much in agreement on that. – Michael Petch Oct 26 '18 at 01:42

1 Answers1

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neg sets all flags identically to what you'd get with a sub from 0.

This sequence of instructions sets all flags (including AF and CF) identically to neg %eax:

xor  %ecx, %ecx
sub  %eax, %ecx     # ecx = 0 - eax

Intel's documentation does actually specify this, but not in the pseudo-code Operation section or in the flags-affected section of the instruction-set reference (Volume 2) entry for neg itself.

The text of the Description section for neg includes this nugget:

This operation is equivalent to subtracting the operand from 0.

And in Volume 1:

7.3.2.4 Comparison and Sign Change Instructions

[a paragraph about CMP]

The NEG (negate) instruction subtracts a signed integer operand from zero.

The existence of this documentation was pointed out by a comment on an earlier duplicate of this question which isn't as directly worded.

I didn't know that vol.1 had a whole section explaining the instructions. It turns out that not everything Intel has to say about individual instructions is in the Volume 2 insn set reference.

There's some evidence that neg decodes internally to the same uop as a sub instruction on Intel CPUs. (e.g. neg [mem] can micro-fuse the load with the ALU op, as well as micro-fusing the store-address and store-data uops. inc [mem] can only micro-fuse the store, so it's 3 total fused-domain uops).

Peter Cordes
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  • *"There's some evidence that neg decodes internally to the same uop as a sub instruction on Intel CPUs."* Interesting… That makes [the behavior I recently questioned](https://stackoverflow.com/questions/44330079/why-does-intels-compiler-prefer-negadd-over-sub) even more surprising. If `neg` is decoded internally as a `sub`, there couldn't possibly be a benefit in `neg`+`add` over `sub`. Perhaps I should officially report this as a bug. Does Intel have an issue tracker? – Cody Gray - on strike Jun 30 '17 at 08:34
  • @CodyGray: I'm pretty sure they accept missed-optimization bug reports in some form. Maybe via forum posts if there isn't a public bug-tracker. I haven't used ICC other than on godbolt. – Peter Cordes Jun 30 '17 at 09:21
  • @tbodt: Turns out it was documented after all, just not where you looked. >. – Peter Cordes Jun 30 '17 at 09:40