I'm reading the data sheet of a network processor SoC. It has a MIPS32 CPU core and many integrated function blocks. When I came across the registers map of one of these blocks, I see that there are many registers whose size is 1 or 2 bytes:
I have always thought that in 32-bit architecture, the register size is always 4 bytes, and the address offsets of registers are always a multiple of 4.
Am I misunderstanding a fundamental concept of computer architecture here?
Those are memory-mapped I/O registers for peripherals built-in to the SoC (the ethernet HW in this case), not "CPU registers".
MIPS has byte load/store instructions, so there's no obstacle to writing a device driver using MMIO on those byte registers. MIPS's lb instruction does a zero-extending byte load into a 32-bit CPU register. Whether you're processing a string one char at a time or writing a device driver that talks to hardware with memory-mapped byte registers, it's all the same.
There is a specific benefit to using byte registers, other than just using less address-space for registers that don't need to be larger: A word load/store can atomically access multiple byte MMIO registers, at least with respect to CPU interrupts. (i.e. the CPU doesn't have to disable interrupts in a pre-emptible kernel device driver to atomically modify multiple related registers).
Related: all modern architectures can natively do byte loads/stores. Early Alpha AXP was the only recent exception, and it has a special sparse I/O region where word loads/stores mapped to byte loads/stores so it could still use normal hardware that had some byte registers, instead of only being able to use ethernet cards designed to be programmed with only word I/O.
