Using the SB_RGBA_DRV primitive in VHDL

Question

I'm having trouble using the SB_RGBA_DRV primitive provided for the Lattice ICE40UP fpga. The Technology Library provides a verilog example which I got to work but when i try using it in VHDL the P&R fails, outputting the following message:

Error: Illegal Connection: Pin 'RGB2' of instance 'myrgb' of type 'SB_RGBA_DRV' should be connected to only one top module port. It is connected to the following terminals : LED2_obuf/DOUT0

This is my .vhdl file:

library ieee;
use ieee.std_logic_1164.all;

entity led is
    port (
        LED0        : out   std_logic;
        LED1        : out   std_logic;
        LED2        : out   std_logic
    );
end entity led;

architecture rtl of led is

component SB_HFOSC is
    port (
        CLKHFEN : in std_logic;
        CLKHFPU : in std_logic;
        CLKHF   : out std_logic 
    );
end component;

component SB_RGBA_DRV is
    generic (
        RGB0_CURRENT: string:="0b000000"; 
        RGB1_CURRENT: string:="0b000000";
        RGB2_CURRENT: string:="0b000000"
    );
    port (  
        RGBPU : in std_logic;
        RGBLEDEN : in std_logic;
        RGB0PWM : in std_logic;
        RGB1PWM : in std_logic;
        RGB2PWM : in std_logic;
        RGB0 : out std_logic;
        RGB1 : out std_logic;
        RGB2 : out std_logic    
        );
end component;

signal int_osc : std_logic;

begin

myosc : SB_HFOSC
    PORT MAP (
        CLKHFEN => '1',
        CLKHFPU => '1',
        CLKHF => int_osc
    );

    myrgb : SB_RGBA_DRV
    GENERIC MAP (
        RGB0_CURRENT => "0b111111",
        RGB1_CURRENT => "0b111111",
        RGB2_CURRENT => "0b111111"
    )
    PORT MAP (
        RGBPU => '1',
        RGBLEDEN => '1',
        RGB0PWM => '1',
        RGB1PWM => '1',
        RGB2PWM => '1',
        RGB0    => LED0,
        RGB1    => LED1,
        RGB2    => LED2
    );

process
    begin
        wait until int_osc'event;
end process;


end rtl;

From a casual reading LED0, LED1, LED2 should be set to IO standard SB_RGBA_DRV in the Pin Constraints Editor. You ought to be able to compare your pin constraints between the Verilog and VHDL versions. The defaults for those physical pins would be SB_OUT_OD. — , May 10 '18 at 21:19

score 2 · Accepted Answer · answered Jun 01 '18 at 23:48

The answer to your question is here:

http://we.easyelectronics.ru/teplofizik/podklyuchenie-vstroennogo-modulya-tokovogo-drayvera-fpga-serii-ice5-ice40-ultra.html

(Scroll down.) Yes, it's in Russian. The key is to add the following declaration at the top of your design file:

library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;

The other things that Teplofizik mentions may be useful to know but aren't entirely necessary.

Your code is almost correct with the above addition. I didn't try to build and run Teplofizik's sample code, but I did modify your code (to actually use the on-chip oscillator) and that code is happily running on an "iCE40UP Breakout" board:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;

entity led is
    port (
        LED0        : out   std_logic;
        LED1        : out   std_logic;
        LED2        : out   std_logic
    );
end entity led;

architecture rtl of led is

-- not necessary - declared in library
--component SB_HFOSC is
--    port (
--        CLKHFEN : in std_logic;
--        CLKHFPU : in std_logic;
--        CLKHF   : out std_logic 
--    );
--end component;
--
--component SB_RGBA_DRV is
--    generic (
--        RGB0_CURRENT: string:="0b000000"; 
--        RGB1_CURRENT: string:="0b000000";
--        RGB2_CURRENT: string:="0b000000"
--    );
--    port (  
--        RGBPU : in std_logic;
--        RGBLEDEN : in std_logic;
--        RGB0PWM : in std_logic;
--        RGB1PWM : in std_logic;
--        RGB2PWM : in std_logic;
--        RGB0 : out std_logic;
--        RGB1 : out std_logic;
--        RGB2 : out std_logic    
--        );
--end component;

signal int_osc : std_logic;
signal count:   unsigned(25 downto 0);
signal led0_en: std_logic;
signal led1_en: std_logic;
signal led2_en: std_logic;

begin

myosc : SB_HFOSC
    generic map(
        CLKHF_DIV => "0b00"     -- 00 = 48 MHz, 01 = 24 MHz, 10 = 12 MHZ, 11 = 6 MHz
    )
    PORT MAP (
        CLKHFEN => '1',
        CLKHFPU => '1',
        CLKHF => int_osc
    );

    myrgb : SB_RGBA_DRV
    GENERIC MAP (
--        RGB0_CURRENT => "0b111111",
--        RGB1_CURRENT => "0b111111",
--        RGB2_CURRENT => "0b111111"
        CURRENT_MODE => "0b0",      -- 0 = full current, 1 = halve the current
        RGB0_CURRENT => "0b000001", -- 4 mA is more than enough
        RGB1_CURRENT => "0b000001",
        RGB2_CURRENT => "0b000001"
    )
    PORT MAP (
--        RGBPU => '1',     -- this is an SB_RGB_DRV parameter
        CURREN => '1',
        RGBLEDEN => '1',
--        RGB0PWM => '1',   -- boring
--        RGB1PWM => '1',
--        RGB2PWM => '1',
        RGB0PWM => led0_en,
        RGB1PWM => led1_en,
        RGB2PWM => led2_en,
        RGB0    => LED0,
        RGB1    => LED1,
        RGB2    => LED2
    );

    -- boring
--process
--    begin
--        wait until int_osc'event;
--end process;

    -- cycle through LED's

    led0_en <= count(25) and count(24);
    led1_en <= count(25) and not count(24);
    led2_en <= not count(25) and count(24);

    count_proc: process(int_osc)
    begin
        if rising_edge(int_osc) then
            count <= count+1;
        end if;
    end process;

end rtl;

I get the error `(VHDL-1240) 'components' is not compiled in library 'sb_ice40_components_syn'` when using this library (Radiant, Synplify Pro). The article (link is dead, here's the [archive link](https://web.archive.org/web/20200225195153/http://we.easyelectronics.ru/teplofizik/podklyuchenie-vstroennogo-modulya-tokovogo-drayvera-fpga-serii-ice5-ice40-ultra.html)) mentions something about it not working with Synplify though, so I tried with LSE, without the library, and it works. The name for the oscillator is `hsosc` and the rgb driver is `rgb` (no SB prefix). — Nicolas, Apr 25 '21 at 18:10
This answer does not work for me. I am using open source toolshain `yosys`, `ghdl-yosys-plugin` and `ghdl`. If I try to call the libraries like suggested here, I get this warning: `spi_icebreaker.vhdl:41:9:error: cannot find resource library "sb_ice40_components_syn"`. This is probably because `sb_ice40_components_syn.vhd` is not freely available and open source tools can't implement it... Source: https://github.com/VHDL/news/issues/19 Some people also use `library ice;` (https://github.com/aoreskovic/TimeSeriesWithXNOR-Net-FPGA/blob/master/top.vhd) but this also does not work for me. — 71GA, Aug 10 '21 at 11:28

score 0 · Answer 2 · edited May 19 '23 at 19:45

0

The answer depends on your toolchain. If using iCEcube2, you'll need to use

library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;

For Radiant,

library ice40up;
use ice40up.components.all;

edited May 19 '23 at 19:45

starball

20,030
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answered May 19 '23 at 19:40

AaronDanielson

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Using the SB_RGBA_DRV primitive in VHDL

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