I am programming on an FPGA and I am wondering what is the implications and differences between a reg and a wire with assignment value.
For example in verilog
reg A;
wire B;
always @ (posedge clock) begin
A = 1'b1;
end
assign B = 1'b1;
What is the main difference in hardware for A and B?
Edit: I have checked that registers use resources of the FPGA but if wiring assignment does not use registers, how are the values obtained?