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I am programming on an FPGA and I am wondering what is the implications and differences between a reg and a wire with assignment value.

For example in verilog

reg A;
wire B;

always @ (posedge clock) begin
A = 1'b1;
end

assign B = 1'b1;

What is the main difference in hardware for A and B?

Edit: I have checked that registers use resources of the FPGA but if wiring assignment does not use registers, how are the values obtained?

1 Answers1

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You asked a wrong question. It should have sounded like:

what is the difference between reg and wire.

reg is a type of data which is supposed to keep its state between transactions. Data of type reg can be assigned a value in always blocks (which contain sequential programming code).

wire is an interconnect media and is intended to connect modules. It is state-less and is not supposed to keep the state and should always be driven. The way to drive them is called continuous assighment and is represented by the assign keyword. Wires cannot assign any value inside always blocks and require assign.

there is another good explanation here: What is the difference between reg and wire in a verilog module

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