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I'm an amateur when it comes to VHDL and hardware in general but I've been working on a project for school and I came across something that I can't understand.

I have a register (type D FF) that's processing a clock signal to store the input value and, in simulation, it works fine if I use a "Force clock" in it's clk input but if I try to "simulate" a clock by manually changing it with "Force Constant" from zero to one and so forth it doesn't "pick up" on the rising edge.

Is this normal behavior? I assumed it would still detect the rising edge when going from 0 to 1.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity register_D is
    generic (
        WIDTH : POSITIVE := 1
    );
    Port ( CLK : in  STD_LOGIC;
           RST : in STD_LOGIC;
           EN : in STD_LOGIC;
           D : in  STD_LOGIC_VECTOR(WIDTH-1 downto 0);
           Q : out  STD_LOGIC_VECTOR(WIDTH-1 downto 0));
end register_D;

architecture Behavioral of register_D is
begin
    process (CLK, RST, EN)
    begin
        if (RST='1') then
            Q <= (others=>'0');
        elsif (rising_edge(CLK) and EN = '1') then
            Q <= D;
        end if;
    end process;
end Behavioral;

Screenshot of me trying to trigger the FF by manually setting the clock (and not working):

Screenshot of me trying to trigger the FF by manually setting the clock

Here you can see it working when I switch clk from "Force constant" to "Force clock":

here you can see it working when I switch clk from "Force constant" to "Force clock".

Mateen Ulhaq
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Cristiano Morgado
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  • I can't remember if it matters, but consider splitting the `EN` stuff in `(rising_edge(CLK) and EN = '1') ` out into a nested if statement. – Mateen Ulhaq Dec 02 '18 at 01:00
  • Can you post the simulation graph? Are you saying that `Q` doesn't get set to `D`? – Mateen Ulhaq Dec 02 '18 at 01:01
  • Q, is a vector so what it does is set all vector elements to '0' since I couldn't do it manully due to it being a generic width vector. This [SO post is where I picked it up from](https://stackoverflow.com/questions/25550244/what-does-others-0-mean-in-an-assignment-statement) – Cristiano Morgado Dec 02 '18 at 01:04
  • This discussion might be relevant: https://stackoverflow.com/questions/15205202/clkevent-vs-rising-edge. That is to say, if your simulation starts at a non-0/1 value, `rising_edge` does not detect any transitions. – Mateen Ulhaq Dec 02 '18 at 01:07
  • [Here's the graph using the manual "force constant"](https://imgur.com/YXBkp06) - notice Q does not change. [Here's the graph when using "Force clock"](https://imgur.com/jLwUXsA). – Cristiano Morgado Dec 02 '18 at 01:14
  • What is the value of your clock at 0ns? As I mentioned, if it starts at a non-0/1 value, `rising_edge` might not detect any transitions from 0->1. (Or at least, that's what I interpretted from the post I linked.) You should probably separate the `(rising_edge(CLK) and EN = '1')` in case it's not synthesizable. I can't remember if it is or not. Let me know of your results. – Mateen Ulhaq Dec 02 '18 at 01:40
  • You don't specify the tool you're using. This is a tool use issue not a VHDL language issue. We can tell this is either Xilinx ISim or Vivado Simulator from the left boundary of the first image. If you add the appropriate tag (xilinx-ise or vivado, possibly xilinx) you may attract experienced or knowledgeable help (as you might in a Xilinx forum). It looks like force constant isn't generating events (in a process in the simulator) while force clock does. Using a testbench for the register works fine. –  Dec 02 '18 at 07:10
  • The difference in behavior between the two force commands corresponds to IEEE Std 1076-2008 10.5 Signal assignment statement, 10.5.2.1 force mode. Where force mode in specifies an effective value force (force constant) and force mode out (force clock) uses the equivalent of force mode out a driver value force (which is scheduled and causes events). It's not possible to use force mode out on a port of mode in. While Vivado Simulator doesn't currently support VHPI, the same mechanism would be used interfacing between an elaborated design hierarchy and simulator, the behavior identical. –  Dec 02 '18 at 15:47
  • In the simulator itself the equivalent of a force mode out would require a process internal to the simulator, for force clock a process driving clock. In VHDL using VHPI this would be contained in a foreign entity. –  Dec 02 '18 at 15:50

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