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What does the PC register point to after fetch is completed?

Is it the address of the next instruction to be executed, or something else?

user366312
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    Does it vary by architecture? BTW, which architecture is being asked about? – donPablo Apr 09 '19 at 22:11
  • @donPablo, both mips and x86. – user366312 Apr 09 '19 at 22:12
  • My AMD x86 manual sez: offset that points to the next instruction within the current code segment. ... ... The contents of this register advance from one instruction boundary to the next. – donPablo Apr 09 '19 at 22:50
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    Can you rephrase this as a computer programming question? What instruction are you executing that depends on the value of PC after fetch? Note that the value made visible to the program usually doesn't match what's happening inside the processor, due to pipelining and superscalar execution. – Raymond Chen Apr 10 '19 at 02:35
  • @RaymondChen: the architectural value of PC / IP during execution of instruction often reflects the microarchitecture of the first-gen implementation of the architecture. e.g. ARM32 has PC = 2 instructions ahead. classic 5-stage MIPS resolved branches in the ID stage right after IF, so relative-branch and segment-absolute `j`ump calculations are relative to the address of the instruction in the branch-delay slot. 8086 could have already prefetched multiple instructions ahead, but presumably at the end of incremental decode it has a pointer to one-past-the-end of the current instruction=PC. – Peter Cordes Apr 10 '19 at 03:32
  • @PeterCordes Right, the architectural value is nowadays not reflective of reality. It wasn't clear what the OP is asking, since it seems to be asking about metaphysical certitude rather than architectural visibility. – Raymond Chen Apr 10 '19 at 03:40
  • @RaymondChen: yeah, agreed the question isn't clear since it's asking about "fetch", which implies asking about microarchitectural implementation. In that case, there isn't a single physical "PC" register in modern superscalar CPUs, the CPU just maintains the illusion of the architectural model of execution. In that case, [x86 registers: MBR/MDR and instruction registers](//stackoverflow.com/a/51522980) is related, but I thought I remembered an answer saying the same thing about PC, that the pipeline associates a PC with each instruction somehow. Maybe I just wrote that in a comment :/ – Peter Cordes Apr 10 '19 at 03:48
  • @RaymondChen: found a duplicate that covers x86 and some others, addressing the difference between architectural and physical that you pointed out. Not MIPS specifically, though. – Peter Cordes Apr 10 '19 at 03:54

1 Answers1

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In x86, the IP register (Intel's name for the PC) doesn't have a clearly defined value except

  • when it is written to the stack by a call, interrupt, or fault, in which case it has the address of the instruction following the last instruction that completed execution.
  • when it is used for IP-relative addressing, in which case it has the address of the instruction following the instruction that contains the IP-relative address.
  • other cases that I won't go into here, such as task switches.

Because of pipelining, in no case is that related to the last instruction fetched. In fact, there can be several instructions with IP-relative addresses being executed at the same time, and each of them uses a distinct IP value in its address computation.

(I presume that the same is true for MIPS, but I can't say.)

prl
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  • Yes, MIPS relative branche (`b*`) and segment-absolute jump (`j`/`jal`) target address calculations are relative to the address of the instruction in the branch-delay slot. (The next instruction *after* the branch/jump). [How to Calculate Jump Target Address and Branch Target Address?](//stackoverflow.com/q/6950230). AFAIK, modern MIPS64r6 pc-relative loads and add-pc to register also use the address of the next instruction. – Peter Cordes Apr 10 '19 at 03:37