How can I use the operation "+" in vhdl?

Question

I have written some code that contains a procedure that does addition operation.I use "+" symbol and compiler does not recognize it.I know that vhdl does not support this symbol, but our professor has asked us to use it in our code.Is there any way I can use "+" without being wrong?

I used all the libraries I know without results. Here is my code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;

package arith_operation is
  constant size: integer :=8;
  constant select_bits: integer :=3;
  procedure add( x,y: in bit_vector(size-1 downto 0);
                 sum: out bit_vector(size-1 downto 0); c_out: out bit );
end arith_operation;

package body arith_operation is
  procedure add
         ( x,y: in bit_vector(size-1 downto 0);
           sum: out bit_vector(size-1 downto 0);
           c_out: out bit) is
  variable s: bit_vector(size downto 0);
  begin
    s:= ("0" & x) + ("0" & y);
    sum:= s(size-1 downto 0);
    c_out:= s(size);
  end procedure add;
end arith_operation;

Here is the error that appears :

Error (10327): VHDL error at arith_operation.vhd(22): can't determine definition of operator ""+"" -- found 0 possible definitions

Use the `unsigned` type (from the `numeric_std` library) to perform additions. Don't use the `std_logic_signed` and `std_logic_arith` libraries. — mkrieger1, Apr 29 '19 at 10:17
@mkrieger1 OP is trying to do arithmetic with bit_vectors, so std_logic_* libraries are irrelevent here. — Tricky, Apr 29 '19 at 10:48

score 0 · Accepted Answer · answered Apr 29 '19 at 10:23

This is because your code has not included any packages that perform arithmetic with bit-vectors. Up until VHDL 2008, there was no package for this. VHDL 2008 introduced numeric_bit_unsigned to allow unsigned arithmetic with bit_vectors, as well as numeric_bit that defines unsigned and signed types using bit. (This is in contrast to numeric_std that has the same types defined using std_logic as the base element type).

You also have the issue of conflicting and non-standard libraries. non-standard std_logic_arith should be removed as it clashes with numierc_std. std_logic_unsigned and std_logic_signed are both non-standard and perform arithmetic using std_logic_vectors, and also define the same functions. Ideally you would not use either library as they are non-standard VHDL, but if you have to use them, its easiest way to use them is only include one or the other, not both. (You can use both, but then you will need to use functions with their full path). You could instead use numeric_std_unsigned that was added in VHDL 2008 for unsigned arithmetic with SLVs.

How can I use the operation "+" in vhdl?

1 Answers1