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In the context of the Intel® 64 and IA-32 Architectures Software Developer Manuals, what exactly is a processor "hint?"

I see it in a few sections:

  1. In the description of PREFETCHWT1 -Prefetch hint T1 with intent to write.

  2. In the SSE4 introduction "The technology also provides a hint that can improve memory throughput when reading from uncacheable WC memory type." Which led to me to this answer regarding WC memory but no clear description of what a hint is.

  3. Next I read one of the SSE4 instructions can perform a load with a "streaming" hint. This led me to the SSE4 Programming reference where I discovered hints can be temporal or non-temporal.

  4. The streaming load hint instruction itself MOVNTDQA "provides a non-temporal hint"

  5. Further into the manual, I find Transactional Synchronization Extensions(TSX) use a "prefix hint" in XACQUIRE and XRELEASE

  6. In the AVX 512 bit section when describing VGATHERPF0DPD and others (there are 7 more of these types of instructions all with the /PS option). In these situations we have either a T0 or T1 hint using dword or qword indices.

  7. The most insightful time I saw hint used in the manual (this list is in order) came in section 10.4.6.1 where it reads

"The non-temporal hint directs the processor to store the data to memory without writing the data into the cache hierarchy."

This is in the 'Cacheability Control Instructions' section involving MOVNTQ, MOVNTPS, MASKMOVQ so would a temporal hint write to a cache line? I'm inferring this as if it's the opposite of a non-temporal hint?

Other links I used in an attempt to piece together the meaning of processor hints:

The Wikipedia page on cache lines ...says hints can prepare, discard, or evict cache lines (also called buffers?). So are hints just instructions that relate to cache lines?

Thank you

Joy
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Robert Houghton
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    A hint is just extra information about some particular usage that the cpu can then use for optimization. Hints can also be ignored. – Jester Jul 30 '19 at 13:01
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    A hint is extra information you provide to help the processor make the right decision when several choices are offered and cannot be decided from context alone (the term is not specific to processors). –  Jul 30 '19 at 13:01
  • example please? – Robert Houghton Jul 30 '19 at 13:02
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    For example, the `MOVNTDQA` is the same as `MOVDQA` except it tells the processor that you will not reuse the value. That is the "non temporal hint". The cpu can then avoid loading the data into the cache. (But you have found that out already.) There were also branch prediction hints that would tell the cpu whether the jump is expected to be taken or not. – Jester Jul 30 '19 at 13:06
  • So are those instructions themselves considered "hints," because they are instructions that deal with the cache? – Robert Houghton Jul 30 '19 at 13:13
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    `MOVNTDQA` itself is not a hint. It has a proper function: it does the data transfer. The hint just provides extra information about how you intend to use the data. `XACQUIRE/XRELEASE` are hints, they are prefixes applied to some other instruction. Also hints don't need to deal with cache. `XACQUIRE` does not deal with cache. Branch hints don't deal with cache. Hints are whatever general information you can pass to the cpu so it can do its job better. It should still be able to perform the same job without the hints but maybe slower. – Jester Jul 30 '19 at 13:16
  • Thank you so much for these words, it's helping but now I'm wondering if a hint is just a thing that optimizes the asm code? Or code in general(C using intrinsics or whatever), so after compilation that program performs better? – Robert Houghton Jul 30 '19 at 13:24
  • Yes that is correct. – Jester Jul 30 '19 at 13:28

1 Answers1

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A hint is part of the operation of an instruction that may not be implemented in the manner described. It may not be implemented at all or it may be implemented in a different way. What exactly the hint does may depend on the specific circumstances in which the instruction is executed. Generally speaking how a hint is implemented doesn't affect the architectural state of the CPU. For cache related hints this means that what exactly ends up in the cache may vary, although for the current processor at least the cache will remain in a consistent state. (Other processors may see memory accesses made by the current processor in an inconsistent order with respect to the normal x86 memory ordering rules, as some hints can violate these rules.)

For example, non-temporal hints tell the processor to avoid using up space in the cache for the given memory reference. They are normally used because the programmer believes that the location in memory isn't going to be accessed again by the CPU, so using the cache would be a waste of space. Writing to video memory is a common example of this, as video memory is almost always used by programs as "write-only" memory.

In practice, non-temporal hints can vary a lot in their operation, depending on the particular CPU, whether or not write-combining (WC) memory used, whether not it's a read or a write, and the specific instruction. See BeeOnRope's answer to a question about non-temporal loads and normal memory for some of the possible differences. Also note that given the asynchronous nature of the caches, the exact behaviour of anything cache related is hard to nail down as prefetching and the actions of other processors can easily evict or bring in cache lines unexpectedly.

Ross Ridge
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