MIPS program that implements the same algorithm in C

Question

Write a complete MIPS program that implements the same algorithm shown below (in C). To verify the output of the MIPS program, copy this C code and execute it.

So I need to convert this C code to MIP code

This is the C code,

int main()
{
  char string[256];
  int i=0;
  char *result = NULL;  // NULL pointer is binary zero

  // Obtain string from user, e.g. "Constantinople"
  scanf("%255s", string); 

  // Search string for letter 'e'.
  // Result is pointer to first e (if it exists)
  // or NULL pointer if it does not exist
  while(string[i] != '\0') {
    if(string[i] == 'e') {
      result = &string[i]; 
      break; // exit from while loop early
    }
    i++;
  }

  if(result != NULL) {
    printf("First match at address %d\n", result);
    printf("The matching character is %c\n", *result);
  }
  else
    printf("No match found\n");
}

And this is my Mips code, I am not sure how to get the input, compare and print the result


.globl main 
.text   
main:
    #$s0 : base address string
    #$s1 : i
    #$s2 : *result

    la $s0, string
    addi $s1, $zero, 0 
    addi $s2, $zero, 0 #*result = null  


    #get input from user
    li $v0 ,8 # take input
    la $a0, string # load byte space into address
    li $a1, 256 #allot the byte space for string
    move $t0, $a0
    syscall
    addi $t9, $s0, $s1 # &string[i]
    lb $t8,0($t9) #t8 = string [i]
while: beq $t8 , 0, outsidewhile # if string[i] == '\0'
    beq $t8, 101, body # if string i == 'e'
    add $s1, $s1,1 #i++
    j while
body: 
    add $t2, $t9, $zero #result = &string[i];   
    j outsidewhile

outsidewhile :
    beq $s2, 0, printaddress # if(result != NULL)
    # printf("No match found\n");
        li $v0,4
        la $a0, msg2        
        li $v0,4
        la $a0, newline 
printaddress:
    #printf("First match at address %d\n", result);
    #printf("The matching character is %c\n", *result);
    li $v0,4
    la $a0, msg     

li $v0, 10 
syscall

.data
string: .space 256
msg: .asciiz "First match at address "
msg1: .asciiz "The matching character is "
msg2: .asciiz "No match found"
endstring: .asciiz "\0"
newline: .asciiz "\n"

I think you are asking about MIPS asm .. not about C.. isn't it?? change tag.. so, others can know it.. — Peter Lee, Nov 26 '19 at 22:53
for C, You can use input function in C standard libray... for ASM, you should link others input library and call it.. — Peter Lee, Nov 26 '19 at 22:55
alright my bad, here is a C code https://notepad.pw/02sb5cg3 — fastmen111, Nov 26 '19 at 22:59
@PeterLee: Most SO questions about MIPS are using MARS or SPIM which simulate a system with toy system calls that can do integer and string input and output with the `syscall` instruction; no library needed. The OP's MIPS code is already using `syscall`. — Peter Cordes, Nov 26 '19 at 23:30

score 0 · Answer 1 · answered Nov 26 '19 at 23:49

0

(thanks for posting it). You appear to be using this definition of system calls (https://www.assemblylanguagetuts.com/mips-syscall-services-table/)

Just after the beq instruction in the while: loop, you increment $s1. I recall that MIPS cpus had a timing bug where it always executed the instruction following a branch. Here, that would mean that $s1 would be one more than you thought it would. The same applies to j while, but that is innocuous since it will be re-executed on loop exit.

The j outsidewhile seems a bit more sinister to me, because the opcode in the delay slot is a branch itself. Not sure how this resolves, but I wouldn't tempt the gods here.

You need to add the code to print the strings, address and character, and probably an exit. Beyond that, it looks ok; but you will have some debugging to do.

answered Nov 26 '19 at 23:49

mevets

10,070
1
21
33

1

Not a timing bug but a design artifact called a branch [delay slot](https://en.wikipedia.org/wiki/Delay_slot). – njuffa Nov 26 '19 at 23:56
1

To someone like the OP who appears to be fairly new to low-level programming, it may well not be recognizable as humor ... – njuffa Nov 27 '19 at 00:01
He should also know that these design flaws should continue to be considered anachronisms. – mevets Nov 27 '19 at 01:22
Jokes have to be funny. Branch-delay slots have a real purpose: fully hide branch latency without needing branch prediction. [Why does MIPS use one delay slot instead of two?](//stackoverflow.com/q/58422262). Anyway, most MIPS code on SO is written for MARS/SPIM with their default setting of simulating a MIPS without a branch-delay slot. (If you don't look at disassembly / machine code, you can pretend it's like an old-school MIPS assembler that reorders your code to fill delay slots, or fills with `nop` if it can't find anything.) – Peter Cordes Nov 27 '19 at 07:46
Of course exposing this classic-MIPS pipeline / microarchitecture detail in the ISA was a burden for later superscalar MIPS implementations that had to preserve the behaviour. That still doesn't make it a "timing bug", it makes it arguably a premature optimization of the ISA for the first-gen microarchitecture. Also why MIPS only has simple branch conditions: single reg `bltz` for example (just the sign bit), or for 2 regs only `beq` and `bne`, not `bgt` or `blt` between 2 regs, [so it only takes 1/2 a cycle](https://stackoverflow.com/questions/56586551) – Peter Cordes Nov 27 '19 at 07:50

Erik Eidt · Answer 2 · 2019-11-27T01:42:38.680

On line 19 of your provided code, you are using addi with 3 register operands. addi requires two register operands and an immediate, so this won't compile/assemble with MARS (I didn't try SPIM).

Your loop fails to (re)load the next byte, so move while: back two instructions: Since you're incrementing $s1, you need to reperform the both add $t9 $s0 $s1 and the lb $t8 ($t9) — otherwise, $t9 doesn't change addresses and $t8 doesn't change byte values either.

MIPS program that implements the same algorithm in C

2 Answers2