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I'm trying to understand the basics but so far I can only see examples with two operands:

ADD <target> <source> means, the values in the <> brackets are summed and stored in < target > . I get this. But how do I read this:

ADD R10 0x8 R5 ?

R5 and R10 mean the addresses in registers, right? What is 0x8?

I would try to transfer as following:

R10 + 0x8 + R5 and store it in R10. Whatever R5, R10 and 0x8 is.

Ben
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    What architecture is this? Please tag your question accordingly. Where did you see the line your're quoting, and in what context? Can you give a link to the original source? – Nate Eldredge Jan 10 '21 at 19:17

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Almost always, 3-operand ISAs are op dst, src1, src2, where dst is write-only instead of also being a source.

e.g. AArch64 add x1, x2, x3 does x1 = x2 + x3, not destroying either of the original input operands.

But for any given ISA, read the manual and it will tell you exactly what each instruction does. I don't recognize the syntax you're using: it's unusual to have a numeric literal constant as the middle operand. I've only ever seen syntaxes that put the immediate as the last source. (Or for op src, src, dst, as the first source). e.g. MIPS addiu $v0, $a0, 123. Omitting commas between operands is a weird thing that some MIPS simulators allow, and maybe standard syntax for some other ISAs including whatever this is.

Peter Cordes
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  • Thank you, I understood the center line but that is enough for me :) Are four operands also possible? Just curious. – Ben Jan 10 '21 at 18:47
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    @Ben: Sure, x86's AVX extension introduces a 4-operand form of [`vpblendvb`](https://www.felixcloutier.com/x86/pblendvb). And arguably, AVX-512 zero-masked and merge-masked instructions are 4 operands, including the mask register even though the syntax is like `vaddps zmm0{k1}, zmm1, zmm2`. There are 4 register-number fields in the overall instruction encoding. See [What kind of address instruction does the x86 cpu have?](https://stackoverflow.com/q/53325275). – Peter Cordes Jan 10 '21 at 18:52
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    Or if you count separate immediate fields as separate operands, PowerPC `rlwinm` has 2 register-numbers and 3 separate immediates for a total of 5 comma-separated operands in the asm source-level syntax. https://www.ibm.com/support/knowledgecenter/ssw_aix_72/assembler/idalangref_rlwinm_rlinm_rtlwrdimm_instrs.html – Peter Cordes Jan 10 '21 at 18:54
  • I guess you're much too advanced for my simple brain but it's interesting to watch/read :) I'll try to understand by reading up a "bit". – Ben Jan 10 '21 at 18:57