Time required to access the memory locations in the same cache line

Question

Consider the big box in the following figure as a cache and the block as a single cache line inside the cache.

The CPU fetched the data (first 4 elements of the array A) from RAM into the cache block.

Now, my question is, does it takes exactly same time to perform read/write operations on all the 4 memory locations (A[0], A[1], A[2] and A[3]) in the cache block or is it approximately same?

PS: I am expecting an answer for ideal case where runtime to perform any read/write operation on any memory location is not affected by the operating system jitter on user processes or applications.

Answer 1

With the line already hot in cache, time is constant for access to any aligned word in the cache. The hardware that handles the offset-within-line part of an address doesn't have to iterate through to the right position or anything, it just MUXes those bytes to the output.

If the line was not already hot in cache, then it depends on the design of the cache. If the CPU doesn't transfer around whole lines at once over a wide bus, then one / some words of the line will arrive before others. A cache that supports early-restart can let the load complete as soon as the needed word arrives.

A critical-word-first bus and memory allow that word to be the first one transferred for a demand-miss. Otherwise they arrive in some fixed order, and a cache miss on the last word of the line could take an extra few cycles.

Related:

• Does cacheline size affect memory access latency?
• if cache miss happens, the data will be moved to register directly or first moved to cache then to register?
• which is optimal a bigger block cache size or a smaller one?