When using typedef to declare a user-defined type, both these forms are accepted by EDA Playground:
typedef reg[4:0] reg5;
typedef logic[4:0] logic5;
However, if doing something similar based on wire type, then this format fails:
typedef wire[4:0] wire5;
I get "Syntax Error".
How can that be explained?
It is illegal to declare a typedef with a wire type, according to the IEEE Std 1800-2017. Refer to section 6.18 User-defined types:
type_declaration ::= // from A.2.1.3
typedef data_type type_identifier { variable_dimension } ;
A wire is not a data_type, whereas reg and logic are. A wire is a net_type.
A typedef defines a datatype that can be applied to a net or variable object kinds. Things are confusing to maintain backward compatibility with Verilog because of implicit definitions.
When you see
logic [4:0] v;
This is implicitly a variable declaration a with an explicit 5-bit 4-state packed array datatype.
var logic [4:0] v;
When you see
wire [4:0] w;
This is explicitly a net declaration a with a 5-bit implicit 4-state packed array datatype.
wire logic [4:0] w;
You can use a typedef for both:
typedef logic [4:0] uint5;
var uint5 v; // var can be implicit
wire uint5 w;
Note that module input and inout ports have wire as the implicit object kind. Also reg and logic are synonyms for 4-state types with logic being the preferred keyword. A reg is not always associated with a register.
