What is False Dependency in CPU?

Question

Can someone help me understand what "false dependency" means?

My professor just explained in this slide why we can't run command 3 before command 1, but why later he called it "False"?

Answer 1

It's "false" because the later instruction doesn't actually need data from earlier instruction. The only conflict is finding a place to put the result. Like the slide says, "not a real data dependency"; only WAR hazards are true dependencies.

If the CPU invents a temporary location to put the result, until the architectural register is available, it can execute the later instruction independently. Having to wait for this register to be ready is something you can avoid, therefore it's not a true dependency, it's false.

Register renaming avoids WAR and WAW hazards in general, except for special cases where the CPU treats an instruction as having an input from a register even though the result doesn't depend on any of the bits there.

Since you tagged this [intel] even though your slide isn't x86 asm, maybe you'd prefer x86 examples:

• Why does mulss take only 3 cycles on Haswell, different from Agner's instruction tables? (Unrolling FP loops with multiple accumulators) - writing the same register with a write-only instruction like movss breaks the dependency on the previous value, since x86 CPUs that do OoO exec also do register renaming. One way to keep multiple vfmadd instructions in flight in a vector dot product is to use multiple registers to hold sums.
• Why does breaking the "output dependency" of LZCNT matter? - lzcnt eax, edx should be write-only for EAX, but Intel Haswell and Broadwell have a false output dependency, scheduling it like bsr eax, edx which does read EAX in case EDX is zero.
• Replacing a 32-bit loop counter with 64-bit introduces crazy performance deviations with _mm_popcnt_u64 on Intel CPUs Same problem but for popcnt, false (output) dependency on Sandybridge-family until Ice Lake. Interestingly, it runs on the same execution unit as lzcnt / bsr / tzcnt / bsf.
• Why doesn't GCC use partial registers? - writing a partial register on many microarchitectures counts as read-modify-write of the full register, e.g. mov di, 123 is scheduled similarly to add edi, 123, unlike mov to a 32 or 64-bit register which both overwrite the whole register to avoid false dependencies without doing messy partial-register renaming.
• Deoptimizing a program for the pipeline in Intel Sandybridge-family CPUs - WAW and WAR false dependencies don't stall on SnB-family, neither do independent writes to the same memory location.