Yosys: Multiple edge sensitivities for asynchronous reset

Question

I am teaching myself verilog, bare with me. :)

I have a clock line called enable coming from a clock divider I created.

I also have a rst button on my devboard.

I would like to modify the following code to react to rst button presses by turning off my leds:

always @ (posedge enable) begin
    if (leds == 8'b11111111) begin
        leds <= 8'b00000000;
    end else begin
        leds <= 8'b11111111;
    end
end

I added my rst button as an additional edge sensitivity and caught it in an if statement:

always @ (posedge enable or negedge rst) begin
    if (leds == 8'b11111111 || ~rst) begin
        leds <= 8'b00000000;
    end else begin
        leds <= 8'b11111111;
    end
end

When I synthesize this for ice40 using yosys, I get the following error: ERROR: Multiple edge sensitive events found for this signal

If it helps, the previous line of yosys output suggests that this always block is translated to a dff cell during synthesis.

I have seen several examples of people including asynchronous resets in their always blocks, so I am curious if somebody can teach me what I am violating in my case, as a novice to verilog/digital-logic.

Thank you so much!

Answer 1

A lot of synthesizers expect the code to follow certain coding styles. If your synthesizer supports async-reset then try making the reset logic exclusive.

always @ (posedge enable or negedge rst) begin
    if (~rst) begin
        leds <= 8'b00000000;
    end else if (leds == 8'b11111111) begin
        leds <= 8'b00000000;
    end else begin
        leds <= 8'b11111111;
    end
end

Your leds == 8'b11111111 || ~rst is logically equivalent. I haven't used a synthesizer smart enough to recognize it as logically equivalent.