Problem : https://hdlbits.01xz.net/wiki/Exams/m2014_q6c
Here is my code
module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);
    parameter A = 000001, B = 000010, C = 000100, D = 001000, 
    E = 010000, F = 100000;
    reg [2:0] next_state;
    
    always @(*) begin
        casez(y)
        6'b000001 : next_state <= w ? A : B;
        6'b00001z : next_state <= w ? D : C;
        6'b0001zz : next_state <= w ? D : E;
        6'b001zzz : next_state <= w ? A : F;
        6'b01zzzz : next_state <= w ? D : E;
        6'b1zzzzz : next_state <= w ? D : C;
        default : next_state <= A;
        endcase
    end
    assign Y2 = next_state == B;
    assign Y4 = next_state == D;
endmodule
I can't understand why this code can't solve the problem. Using this code, Y2 and Y4 are stuck at GND. I think there's a problem with "casez", but I am not sure.
Could you give me a correct answer and tell me the reason?