Questions tagged [instruction-encoding]
99 questions
35
votes
3 answers
How to read the Intel Opcode notation
I am reading some material which quotes Intel's vol.2 SDM x86 manual about opcodes and machine-code encoding of assembly instructions, but I cannot understand what things like cw, cd, /2, cp, or /3 mean following the opcode byte.
E8 cw CALL rel16…
asher
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19
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3 answers
How encode a relative short jmp in x86
Suppose I want to do a short jump using the EB opcode, jmp rel8 short jump
Intel manual entry for it:
EB CB or JMP rel8
"Jump short, RIP = RIP + 8-bit displacement sign
extended to 64-bits"
(where CB is a byte signed value representing the…
user1629569
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18
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2 answers
Is there an x86 opcode for moving an immediate byte to a direct memory location (without using registers)?
Is there a way to 'mov'e a specific immediate byte-size number into a direct memory location? I.e.
MOV 10h,ffffh
to write the value 16 into the memory address 65535? If so, which opcode is that, orwould I have to store a memory address into a…
Nicholas Hill
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13
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3 answers
Why does jmpq of x86-64 only need 32-bit length address?
As I use objdump -D to disassemble a binary, the typical code of jmpq is like e9 7f fe ff ff, which is used for representing a negative offset. However, the address of x86-64 is 64(48)-bit (to my knowledge), so how can this 32-bit address 7f fe ff…
WindChaser
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11
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6 answers
How to tell the length of an x86 instruction?
I was looking at the different instructions in assembly and I am confused on how the lengths of different operands and opcodes are decided upon.
Is it something you ought to know from experience, or is there a way to find out which operand/operator…
user277465
10
votes
2 answers
x86 find out operand size of instruction given only the hex machine code?
For example, given a hex: 83 E4 F0
By looking at the intel developer's manual, I can figure out that 83 means and and FO means the -16. Looking at E4, I can decode that the source/destination register is either SP or ESP.
Therefore, I can conclude…
Hery
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8
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1 answer
How does an instruction decoder tell the difference between a prefix and a primary opcode?
I'm trying to wrap my head around the x86 instruction encoding format. All the sources that I read still make the subject confusing. I'm starting to understand it a little bit but one thing that I'm having trouble with understanding is how the CPU…
Daniel Catalano
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8
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1 answer
x86 XOR opcode differences
looking at http://ref.x86asm.net/coder32.html I found two opcodes that match for the statement
xor eax,eax
1) opcode 31 XOR r/m16/32 r16/32
2) opcode 33 XOR r16/32 r/m16/32
both refers to 32bit register for operand1 and operand2. So,…
Maverick
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7
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x86 multi-byte NOP and instruction prefix
As a small recall, the x86 architecture defines 0x0F 0x1F [mod R/M] as a multi-byte NOP.
Now I'm looking at the specific case of an 8-byte NOP: I have got
0x0F 0x1F 0x84 0x__ 0x__ 0x__ 0x__ 0x__
where the last 5 bytes have got arbitrary values.
The…
ayekat
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6
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2 answers
Why does JALR encode the LSB of the offset?
We know that jal specifies a 21-bit offset. However, it does not encode a 21-bit offset but a 20-bit one. The reason is that the least significant bit of an address is always zero because the smallest possible RISC-V instruction is 2 bytes, so this…
Lui
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5
votes
1 answer
Forcing a JMP rel32
If I do something like (dummy example):
jmp 1f
1: ret
on gcc/clang it generates a short relative jump because the label is near.
I'm curious, is it possible to force a JMP rel32 regardless of the label's distance?
Petr Skocik
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5
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1 answer
Why doesn't MIPS have a Store Immediate instruction just like Load Immediate instruction?
MIPS has a Load Immediate (LI) pseudo instruction to load a 32-bit immediate value into a register. But it does not have Store Immediate (SI) instruction to store a 32-bit immediate value to Memory. Can someone explain me why?
sandywho
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5
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2 answers
What are 8086 ESC instruction opcodes
Mostly of a historical interest and if I were to implement 8086 compatibility for assembler, what operands are considered valid for ESC instruction?
ESC opcode, source
From 8086 Programmer's manual I know, that opcode is an immediate in range 0 to…
Alexander Zhak
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Are these push r16 encodings correct under 64BIT mode?
About push wordregister(r16) under 64BIT mode of Intel x86_64 CPU.
In B-28, Vol. 2D,
APPENDIX B, INSTRUCTION FORMATS AND ENCODINGS,
Intel Combined Manual PDF,
Order Number: 325462-080US, June 2023.
Table B-15. General Purpose Instruction Formats and…
YutakaAoki
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4
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1 answer
Where has Intel documented the encoding of extended registers (R8-R15) in ModR/M byte?
I'm using the latest official "Intel® 64 and IA-32 Architectures Software Developer’s Manual Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D and 4" as a reference to understand the machine level encoding of x86-64 ISA.
The documentation for the…
John Adam
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