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Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

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Difference between 1 and 1'b1 in Verilog

What is the difference between just giving 1 and giving 1'b1 in verilog code?
Yashwanth Gopinath
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Reload VCD file in gtkwave from command line

I am using a VCD file generated by iverilog with gtkwave. There is a button present in the GUI, but I would like to reload the wave window from the command line. How would I go about that?
user7426532
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I'm getting this error for my verilog code, "Illegal operation for constant expression"

when ever I compile this code, I get the following errors. module mv2_generate ( input [127:0] c_array [1:0], input [127:0] p_array [1:0], input [127:0] p1_array [1:0], output reg [15:0] min_mv ); //genvar index; integer a, b,…
Kunal Bambardekar
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SystemVerilog support of icarus (iverilog compiler)

I am using iverilog on a Mac, and I have problem compiling some codes that include always_ff and always_comb blocks. ModelSim compiles those codes without any problem. Is it possible to configure iverilog so as to support always_ff and always_comb…
k.rallis
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Icarus Verilog syntax error when subtracting two 32-bit inputs?

I am having a very frustrating experience with my first week learning Verilog. I am trying to compile the below code - from mipsalu.v module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; …
Zabitz
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Verilog with cocotb : assign statement

My Verilog code is an adder that just uses assign sum = a+b. The problem is that, while running it using cocotb, sum remains unknown, though a and b have valid values. When I make sum a reg type, it works. `timescale 1 ns / 1 ps module adder(input…
n.r
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How do I run the verilog code on a testbench?

I wrote the code for a ripple carry adder. Testbench is also available. How do I run this test bench on my Verilog code? I don't have a simulator. I am using the iverilog compiler. ripple_carry_adder.v module half_adder(a,b,sum,carry); input…
sudeepdino008
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Emacs Verilog 'compilation exited abnormally with code 255'

module FullAdder (a, b, ci, r, co); input a, b, ci; output r, co; assign r = a ^ b ^ ci; assign co = (a&b) | ((a^b)&ci); endmodule // FullAdder module adder_4bit (A, B, ci, R, co); input [3:0] A, B; // [MSB:LSB] input ci; …
Hyeonsu Shin
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iverilog Not Compiling Multiple Port Declarations With Multiple Bits Written In One Line

I am trying to compile Verilog code with a testbench with the last stable version of iverilog 11.0; here is an example: iverilog -o example example.v tb_example.v // example.v module example( input [1:0] input1, [1:0] input2, // problem is…
Celuk
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Error compiling code due to direction declaration

I am running code from the internet using iverilog as follows: example.v module example (A,B,C,D,E,F,Y); wire t1, t2, t3, Y; nand #1 G1 (t1,A,B); and #2 G2 (t2,C,~B,D); nor #1 G3 (t3,E,F); nand #1 G4 (Y,t1,t2,t3); endmodule and…
Aschoolar
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Icarus Verilog warning $readmemh: Standard inconsistency, following 1364-2005

I'm trying to read a memory file using $readmemh, but I'm not sure what the correct file format is since I'm seeing a warning. In my testbench, I have the following: reg [7:0] progmem [4095:0]; initial begin $readmemh("progmem.txt",…
Peter
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Verilog unsigned non-restoring division. Syntax Error: "I give up" Icarus Verilog

I wanted to know why my Iverilog Compiler throws the "I give up" error at the end of the module. The error is: DivisionsSchaltwerk.v:64: syntax error I give up There is the Verilog code for my Divisior using a changed version of the AQ shift…
Mark Lauer
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Why is iverilog complaining about this expression/port width?

I have a confusing Verilog error that is coming up as I am trying to make a 5 bit 2x1 MUX using STRUCTURAL code and I can't seem to find any info on why my code would be showing up wrong. The error is: error: Expression width 5 does not match width…
Barnabas Bullion
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How is iverilog simulator interpreting my RAM code to determine 'x' values?

I am attempting to write and test a simple 16-bit width RAM8 chip in Verilog using Icarus Verilog. I'm finding it difficult to understand conceptually why the iverilog simulator is showing me 'x' (undefined) values on certain clock ticks and…
Isaiah Becker-Mayer
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Can i assign 2 state out of bound accessed bits to 4 state variable?

Should this produce x or 0 and thus the result be completely x or 0? Acc. to LRM if we access 2 state variable out of bound then it should be 0. Is it correct to assign 0 to r2. module top; reg [1:0] r; bit [1:0] b; assign r2= b[2:1]…
subh
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