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Questions tagged [spartan]

Spartan is a FPGA family of Xilinx. It has different generations e.g. Spartan-3, Spartan-6.

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Spartan Programming

I really enjoyed Jeff's post on Spartan Programming. I agree that code like that is a joy to read. Unfortunately, I'm not so sure it would necessarily be a joy to work with. For years I have read about and adhered to the "one-expression-per-line"…
Luther Baker
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SP605 Spartan 6 DDR3 addressing

the following post is quite long, but since I have had trouble making the SP605 board properly interact with the DDR3 for over a month now, hopefully this will be useful to others in the same situation as I find myself in. I am pretty certain it's a…
buped82
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Alternative method for creating low clock frequencies in VHDL

In the past I asked a question about resets, and how to divide a high clock frequency down to a series of lower clock square wave frequencies, where each output is a harmonic of one another e.g. the first output is 10 Hz, second is 20 Hz etc. I…
davidhood2
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Increasing the speed of Xilinx ISim simulation

I have a large ISim design for Spartan-6 using about 6 of the Spartan-6 FPGA IP cores. It needs to run for a simulation time of 13 seconds, but at present takes 40 seconds to run a simulation time of 1 ms. During the 13 seconds it will also write…
davidhood2
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Examples of Spartan Programming in C#

I am interested in reading examples of code in C# that makes use of the Spartan Programming philosophy. Can you please provide a link to any open source project or online code sample that follows this coding style?
Tangiest
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shortening type names in java

Is there a way to shorten type names in java. Something similar to typedef in c++ or similar to the usage of namespaces? For example if I have the type "org.w3c.dom.Node" and I don't want to write that full name every time, but also don't want to do…
tomermes
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Serial communications with Digilent Atlys board

I have an Atlys board http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS with Spartan6 FPGA on it. I want to setup serial port communications with host PC via onboard USB-UART bridge by EXAR. Everything's ok when running…
Andrey Pesoshin
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rising_edge() vs process sensitivity list

I've been developing in VHDL for a while in a University course and I thought that I understood how it worked, but once in a while I realize that I quite not actually understand it. Here goes my question: As I could understand, if a signal is in a…
user3013172
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ISE Design Suite 14.7: ISE® Spartan®-6 Virtual Machine (VM) for Windows 10

I installed Xilinx ISE 14.7 on Windows 10. When I try to open Project Navigator it opens in a Linux Virtual Machine (VM). It means Xilinx setup installs a VM environment in windows 10. Is it possible to install ISE Design Suit in windows 10 instead…
Chand Baba
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FPGA : using both falling and rising edge in same process

I'm a fpga & vhdl newbie.. My development environment is as follows. FPGA :Spartan 6 XC6SLX9 Compiler : ISE 14.04 Simulator : Isim I'm making a simple counter, but there are some things I can't understand. The following code is what I wrote. What I…
YJ Kim
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How to store data and program permanently in an FPGA?

From what I surfed, once the power goes off in an FPGA you've to program it again. But I'm trying to implement an FPGA based security system using verilog. In that, I want the password of the system to be permanently stored i.e. even when the power…
Adithya Vasudevan
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Failed to open JTAG cable

I'm using an Atlys Spartan-6 xc6slx45 board. I am unable to burn the bit file using SDK. When I try to program FPGA it shows these errors: Program FPGA failed Connection to Board Failed Failed to Open JTAG Cable Cable target is not…
Classe Ensi E
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Xilinx ISE 9.2 and programming FPGA

Can anyone tell me how should I configure Xilinx ISE to get fastest FPGA programming speed ? I have Spartan 3 Starter Board (FPGA chis is xc3s200). I'm not sure what's the name of programming cable, but I plug it in my computer to LPT1 (parallel…
xx77aBs
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Why does my VHDL countdown timer on Nexys3 FPGA board switch between 59 and 68?

I created a 60 second countdown timer in VHDL and connected it to the 7-seg displays on a nexys3 FPGA boar but it doesn't work. This is a project for my college class. I'm not really skilled at VHDL or digital electronics at all, but I've managed to…
Goran Orsolic
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Difficulties to establish a communication between a Spartan 6 FPGA with a Mini PCIe bus and ARM-cortex A9 (IMX6 architecture)

I’m trying to establish a communication between a Spartan 6 FPGA with a Mini PCIe bus and a board containing an ARM-cortex A9 (IMX6 architecture) running Linux kernel 4.13. I want to use RIFFA to communicate between the Spartan 6 FPGA and the…
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