How to interpret the parameters in a DIMM datasheet?

Question

I am trying to understand the internal layout of my DDR4 DIMM. Such as:

• rank number
• bank number
• row/column of the memory array within a bank

According to intel customer script, the reported DIMM parameters are like this:

From this post I know that:

• DR = Dual Rank
• x4 means the DRAM chip has a physical channel of 4-bit width (please correct me if I am wrong about this.)

Then I searched for the part number M393A4K40BB1-CRC and found the Samsung Production Selection Guide. It says this for this part number:

And I found the datasheet. It says this:

So it basically says the DDR4 module M393A4K40BB1-CRC is made of DDR4 SDRAM component K4A8G045WB-BC##. And as I checked the pyhsical DIMM, it is indeed that componnet. But I simply cannot find this K4A8G045WB-BC## component in the previous componnet table. I think this is a doc error.

But anyway, what I really care about is how to derive the bank, row, column info from this sheet?

And how to interpret below parameters from the datasheet?

From the Component table:

• 1G x 8

From the Module table:

• 4G x 72
• 8Gb(2Gx4)*36

It seems x and * have different meanings. What's the difference?

ADD 1

According to the book Memory Systems by Bruce Jacob.

So it seems the x4 x8 represents the device width, which means how many arrays an independent bank contains. An array can contribute a single bit when specifying a row and a column. A bank can contain multiple arrays so that it can contribute multiple bits when specifying a row and a column.

The calculation is like this for the first row:

Capacity = 1 rank x 16 devices/rank x 4 banks/device x 4 arrays/bank x 4K rows x 1K cols = 1024Mb = 128MB

Explanation for the 1st row, from the lowest level (array) to the highest level (memory module):

1. Each array contains 4096 * 1024 = 4M bits (Number of Rows and Columns)

2. Each bank contains x4 arrays, that is 4M * 4 = 16M bits (Device Width)

3. Each device contains 4 banks, that is 16M * 4 = 64M bits (Number of Banks)

4. Each Rank contains 16 devices, that is 64M * 16 = 1024M bits (Devices per Rank)

5. Each SDRAM memory module contains 1 rank, that is 1024M * 1 = 1024M bits = 128M Bytes

Device Density = 4 banks/device x 4 arrays/bank x 4K rows x 1K cols = 64Mb

Device Density refers to the bullet 3 above.

ADD 2

A quote from the above book:

...a x4 DRAM (pronounced “by four”) indicates that the DRAM has at least four memory arrays and that a column width is 4 bits (each column read or write transmits 4 bits of data). In a x4 DRAM part, four arrays each read 1 data bit in unison, and the part sends out 4 bits of data each time the memory controller makes a column read request.

Below diagram clearly illustrates how the column width and bank numbers are related logically.

Note that each of the DRAM illustrations in Figure 7.4 represents multiple arrays but a single bank. Each set of memory arrays that operates independently of other sets is referred to as a bank, not an array.

And:

A system is composed of potentially many independent DIMMs. Each DIMM may contain one or more independent ranks. Each rank is a set of DRAM devices that operate in unison, and internally each of these DRAM devices implements one or more independent banks. Finally, each bank is composed of slaved memory arrays, where the number of arrays is equal to the data width of the DRAM part (i.e., a x4 part has four slaved arrays per bank).

When it comes to the memory jargons, there are so many confusion...

Answer 1

My current understanding:

• 8Gb(2Gx4)*36

  According to here:

The expression "8M x 8" describes one kind of 64Mbit chip in more detail. In the memory industry, DRAM chip densities are often described by their cell organi-zation. The first number in the expression indicates the depth of the chip (in locations) and the second number indicates the width of the chip (in bits). If you multiply the depth by the width, you get the density of the chip.

So the whole expression means 36 DRAM device/chips make up a DIMM (32 for storage and 4 for ECC). Each DRAM device/chip's density is 2Gx4 = 8Gb. 2G means the total locations. x4 means each bank in the device/chip has 4 arrays, which contributes 4bits for a location. The geometry details such as row, column and bank are not recoverable from this description.

• 1G x 8

  This means the DRAM device 1G locations with each location contribute 8 bits.

• 4G x 72

  This describes the DRAM module instead of single DRAM device/chip. But in a similar way. The 4G is the module depth in location count. And each location contributes 72 bits (I think 8bits are for ECC). So the module capacity is 4Gx64 bits = 32GB.

So the take away is: location count * location size = total size. This formula is used for both device density and module capacity notation.

Answer 2

The x4s and x8s refer to the number of banks on the memory component or chip. This number (not the one of individual memory chips on a PCB) gives the Rank of the memory module. So if a module has chips on both sides of the PCB (making it dual-sided), it can still be Single Ranked, Dual Ranked (like in your case), or Quad Ranked, depending on how those chips are engineered.

A Rank (which means a data block) is currently 64 or 72 bits. A module made from x4 chips will need 18 chips for one Single Rank (18 x 4 = 72, 72/72 = 1). This is the *18 in the table.

A module made from eighteen (*18) x8 chips would be Dual Ranked (18 x 8 = 144, 144/72 = 2).

Since yours has x4 and is DR, it will need *36 chips of the x4 type for it to be DR. (36 x 4 / 72).

Identically, A module that has 36 x8 chips becomes Quad Ranked (36 x 8 = 288, 288/72 = 4).

So basically, the xN is the number of banks, the *NN is the number of chips.