From the very little knowledge i have, every PCI device has 4 interrupt pins. Pins from the many different PCI devices on the motherboard (Built-in or external devices) are routed to an IO-APIC (Advanced programmable interrupt controller) through a programmable interrupt router. So that was the topology.
As far as i know when an interrupt occur, the IO-APIC will be signaled and it will raise an INT to the CPU then magic happens and CPU starts executing an ISR (Interrupt Service Routine).
What was that magic ?
What is the communication that should happen between the CPU and the IO-APIC to handle the INT ?
I mean how does the CPU received the interrupt vector (is it a special PCI bus cycle ?) & what will happen if the the IRQ was shared by many devices (Take x86 Linux as a platform reference) ?
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Karim Manaouil
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The interrupt vector is already stored in the interrupt vector table, so the CPU doesn't need to get it from a peripheral. If the interrupt is associated with an IO-APIC or similar device that can raise interrupts for different reasons, the interrupt handler will query that device to find out why it raised the interrupt. There's no special bus cycle for this, it's the same way a CPU would get any information from one of its peripherals.
David Schwartz
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