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I had the unfortunate experience of failing a memtest today, but the results seem a bit peculiar and I have several questions about them. Of course this will probably end in me returning the RAM, but I still want to understand what went wrong.

Memtest log pastebin.

What I noted was peculiar was that across multiple addresses, it was always the last bit of the first byte that failed. Here is a section of the log showing this.

2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 1, Address: 252A019F8, Expected: FEF7FFFF, Actual: FFF7FFFF
2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 1, Address: 253201A38, Expected: FEFEFFFF, Actual: FFFEFFFF
2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 2, Address: 255641A98, Expected: FEF7FFFF, Actual: FFF7FFFF
2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 2, Address: 255E41CB8, Expected: 00000000, Actual: 01000000
2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 2, Address: 257641A78, Expected: FEF7FFFF, Actual: FFF7FFFF
2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 2, Address: 257E41C98, Expected: 00000000, Actual: 01000000
2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 3, Address: 259201A58, Expected: FEFEFFFF, Actual: FFFEFFFF
2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 3, Address: 259201B58, Expected: FEEFFFFF, Actual: FFEFFFFF
2018-01-27 07:19:35 - [MEM ERROR - Data] Test: 6, CPU: 3, Address: 259645310, Expected: 01004000, Actual: 00004000
2018-01-27 07:19:36 - [MEM ERROR - Data] Test: 6, CPU: 3, Address: 259A01A18, Expected: FEFFF7FF, Actual: FFFFF7FF
2018-01-27 07:19:36 - [MEM ERROR - Data] Test: 6, CPU: 3, Address: 259A01AD8, Expected: FEFFBFFF, Actual: FFFFBFFF
2018-01-27 07:19:36 - [MEM ERROR - Data] Test: 6, CPU: 3, Address: 25B201A38, Expected: FEFEFFFF, Actual: FFFEFFFF
2018-01-27 07:19:36 - [MEM ERROR - Data] Test: 6, CPU: 3, Address: 25B201B38, Expected: FEEFFFFF, Actual: FFEFFFFF

I tested the RAM across two different computers and resulted in the same error. Do these results tell me anything about the error in internal logic that is happening? I would think it's because a set of bytes share the same addressing logic, but I would expect the failures to be sequential in memory bytes then. Or could it be that the failing bit across all of these addresses is the same and for some reason the same byte is given a different address every rerun?

Secondly, the memtest only failed a few tests, specifically it did not fail tests 0 through 2, even after multiple memtests. I only have basic knowledge of what each test does but I am surprised that the first few tests never resulted in an error. Any reason why?

Kamil Maciorowski
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Styil
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This may be because of the layout described in this Wikipedia article: row hammer.

In dynamic RAM (DRAM), each bit of stored data occupies a separate memory cell […]

Memory cells (blue squares in the illustration) are further organized into matrices and addressed through rows and columns. A memory address applied to a matrix is broken into the row address and column address, which are processed by the row and column address decoders (in the illustration, vertical and horizontal green rectangles, respectively). After a row address selects the row for a read operation (the selection is also known as row activation), bits from all cells in the row are transferred into the sense amplifiers that form the row buffer (red squares in the illustration), from which the exact bit is selected using the column address.

image

Picture source (public domain)

Hypothesis: there's something wrong with one bit of a certain row buffer (red squares); it affects reading of any row the buffer corresponds to. I'm not claiming it will happen every time, for every row and any written data; yet I believe this matrix form and row buffer (or something similar) have something to do with the fact it's always the last bit of the first byte that failed.

Secondly, the memtest only failed a few tests, specifically it did not fail tests 0 through 2 […]. I am surprised that the first few tests never resulted in an error. Any reason why?

This manual explains what the tests are:

  • Test 0 [Address test, walking ones, no cache]

Tests all address bits in all memory banks by using a walking ones address pattern.

  • Test 1 [Address test, own address, Sequential]

Each address is written with its own address and then is checked for consistency. In theory previous tests should have caught any memory addressing problems. This test should catch any addressing errors that somehow were not previously detected. This test is done sequentially with each available CPU.

  • Test 2 [Address test, own address, Parallel]

Same as test 1 but the testing is done in parallel using all CPUs and using overlapping addresses.

I understand tests 0-2 are designed to catch addressing errors, not necessarily actual data errors. Note if they were able to catch all errors then further testing wouldn't be needed.

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Kamil Maciorowski
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