How to understand another lspci tree format?

Question

I can understand this lspci output

But， I cannot understand this：

// lspci -tv 
-+-[0000:d7]-+-05.0  Intel Corporation Sky Lake-E VT-d
 |           +-05.2  Intel Corporation Sky Lake-E RAS Configuration Registers
 |           +-05.4  Intel Corporation Sky Lake-E IOxAPIC Configuration Registers
.......
 |           +-16.4  Intel Corporation Sky Lake-E M2PCI Registers
 |           +-16.5  Intel Corporation Sky Lake-E DDRIO Registers
 |           +-17.0  Intel Corporation Sky Lake-E M2PCI Registers
 |           \-17.1  Intel Corporation Sky Lake-E DDRIO Registers
 +-[0000:ae]-+-05.0  Intel Corporation Sky Lake-E VT-d
 |           +-05.2  Intel Corporation Sky Lake-E RAS Configuration Registers
 |           +-16.5  Intel Corporation Sky Lake-E DDRIO Registers
......
 |           +-17.0  Intel Corporation Sky Lake-E M2PCI Registers
 |           \-17.1  Intel Corporation Sky Lake-E DDRIO Registers
 +-[0000:3a]-+-00.0-[3b-3d]----00.0-[3c-3d]----03.0-[3d]----00.0  Intel Corporation Ethernet Connection X722
 |           +-05.0  Intel Corporation Sky Lake-E VT-d
.....
 |           +-0d.2  Intel Corporation Sky Lake-E LMS Channel 2
 |           \-0d.3  Intel Corporation Sky Lake-E LMDP Channel 2
 +-[0000:17]-+-00.0-[18]----00.0  Device baec:baec
 |           +-02.0-[19]--+-00.0  Mellanox Technologies MT27710 Family [ConnectX-4 Lx]
 |           |            \-00.1  Mellanox Technologies MT27710 Family [ConnectX-4 Lx]
 |           +-05.0  Intel Corporation Sky Lake-E VT-d
.....
 |           \-1e.6  Intel Corporation Sky Lake-E PCU Registers
 \-[0000:00]-+-00.0  Intel Corporation Sky Lake-E DMI3 Registers
             +-04.0  Intel Corporation Sky Lake-E CBDMA Registers
......
             +-1f.4  Intel Corporation C620 Series Chipset Family SMBus
             \-1f.5  Intel Corporation C620 Series Chipset Family SPI Controller

This is an Intel CPU

Model name:            Intel(R) Xeon(R) Platinum 8255C CPU @ 2.50GHz

ls /sys/class/pci_bus/
0000:00  0000:02  0000:17  0000:19  0000:3b  0000:3d  0000:80  0000:ae
0000:01  0000:03  0000:18  0000:3a  0000:3c  0000:5d  0000:85  0000:d7

Question

What is the origination of the buses(d7,ae,ae,17,00)?

Answer 1

I found the anwer here

Nowadays multi-processor systems is becoming more and more common especially in high performance computing.

Things become interesting when you think about it from PCI Bus perspective: We use to model it as one PCI host bridge (root complex) yet now we may face the case where there are multiple PCI root bridges.

So yes root bridge is no longer the “root” or at least not the only “root” and we have to move away from the simple logic of assigning Bus 0, Device 0, Function 0 to that device.

What’s more, now they may each can connect to their own pool of memory chipsets how would you decide on what memory/io resource range to give to each of them?