CISC and VLIW, and instruction and opcode

Question

From http://en.wikipedia.org/wiki/Instruction_set

CISC processors include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are typified by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor.

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In very long instruction word (VLIW) architectures, which include many microcode architectures, a single instruction includes multiple simultaneous opcodes and their operands.

CISC and VLIW seem to me the same concept, in that an instruction includes multiple operations (i.e. opcodes). So are they the same concept?

How do you define a single operation (i.e. opcode) is, when telling if an instruction has multiple operation (i.e. opcodes)?

Answer 1

Modern CISC processors have multiple execution units. They also have a lot of extra circuitry and logic to try and distribute the instruction stream amongst those execution units.

VLIW is an attempt to have the compiler do some of this work and use the saved circuity for even more execution units, cache or other resources.

An example would be Itanium in which instruction words are 128bits and contain three instructions. This lets the compiler do some of the work in pairing up instructions to execute together.

Answer 2

An instruction is a single order that must be done logically before the next one. If an instruction contains more than one operation, such as in a VLIW instruction, these are meant to be done at the same time. And in a VLIW instruction each operation slot corresponds to a hardware processing unit (a combination of a FPU and an ALU) these are statically assigned by the instruction. Where as in a CISC or RISC the processor may choose any free processing unit. But as the units are assigned in the instruction with VLIW, you can't run code for one VLIW on another model with greater or fewer processing units as the instructions for that would have more or less slots in their instructions, although some greater ones might allow running code that uses a format which has fewer slots, unlike in a CISC or RISC where the code can automatically use additional processing units, the VLIW code can't use the extra processing units without being recomplied specifically for the processor.

That limitation with VLIW is what prompted Explicit Data Graph Execution (EDGE).

Answer 3

How do you define a single operation (i.e. opcode) is, when telling if an instruction has multiple operation (i.e. opcodes)?

The definitions and your expectations are not quite correct. "Opcode" is used for indicating visible instructions, not hidden operations like micro-ops, and "instruction" should only refer to user-exposed operations. An "operation" does not corresponds to an opcode and may be simple (a single opcode) or complex (multiple opcodes) depending on how you refer to it, like if you want to address the whole operation itself, or address each lower level operation used to achieved that big thing. It's just like when you do a division, it can be called a single operation. But division can also be subdivided into a series of subtractions/multiplications, i.e. multiple operations (stages in hardware term). Many old RISC architectures have separate instructions for various stages of a division to keep the instructions simple and make pipelining straightforward. But modern RISC architectures typically don't do that and can have very complex instructions like CISC, for example rlwinm in PowerPC or ldm/stm in ARM.

In VLIW architectures, a single instruction is still 1 instruction. However, instructions will be grouped together as a batch. For example, a batch in Itanium architecture contains 3 instructions that will be run at the same time. Of course each instruction must have its own opcode, and those opcodes are available to the programmer to use. Moreover those instructions are independent of the others, unlike micro-ops which jointly represents an operation of some higher level instruction. For example in some architecture you may have 2 additions along with a multiplication and a bitwise xor of different things in a batch that doesn't relate to each other.

On the contrary, a CISC instruction is only one instruction that does a single operation, and has one opcode. Prior generations of CISC CPUs execute each instruction directly, so it's really a single unbreakable instruction. However in modern processors, complex "operations" will be divided into multiple simpler micro-operations that can be done in shorter clock cycles. Those micro-ops are not visible to outsiders, so you can't call them multiple opcodes. To users, it's still a single instruction. You will probably never know which micro-ops Intel or AMD is using under the hood. Besides a CISC instruction can be broken into a single micro-op or multiple ones, so it's completely wrong to say CISC includes multiple operations in a single instruction.

In fact modern RISC architectures also break instructions into micro-ops just like CISC, and very simple operations are also combined together into a macro-op that's also not user-visible, for example CMP/Jcc in x86 or DIV/REM in RISC-V and you won't say that RISC is simple. A RISC instruction can still do multiple operations.

CISC and VLIW, one has a single instruction with a single opcode running at a time (barring superscalar and out-of-order execution for now), one executes multiple instructions at a time, so how are they the same concept? You should view on top of the instruction set or at least the same level. Comparing a thing used internally in a CPU with a thing on the instruction set above the CPU is meaningless.