I am trying to clear some confusion regarding instruction set architecture and how memory is accessed. Basically I know that in byte addressable memory, data is stored byte by byte either in big-endian or little-endian. Now if we have a 32 bit processor, meaning that we could use 32 bit registers; do data buses transfer 4 bytes of data at a time at each clock cycle? Also, are the instructions also 32 bits long? How does that affect the opcode size versus the operand size?
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do data buses transfer 4 bytes of data at a time at each clock cycle?
This is entirely up to the system design, but I'm gonna say yes, they transfer 4 bytes of data at each clock cycle (if they are instructed to, ofcourse) assuming that you are a computer engineering/science student taking a computer organization/architecture class. However, this might not always be the case as contemporary computer architectures are far more sophisticated than what you see in your computer organization/architecture course.
I recommend you to read Everything you need to know about DDR, DDR2 and DDR3 memories so that you can have an idea how double data rate transfers occur.
Also, are the instructions also 32 bits long?
Not necessarily. It's up to the design system. I recommend you read about RISC and CISC architectures.
[Source] For example, A Complex Instruction Set Computer (CISC) with IA-32 (namely Intel i386 architecture) might have instructions of length 1 byte to 12 bytes (8 bits to 96 bits) while it has 32-bit data registers.
How does that affect the opcode size versus the operand size?
Again, completely up to the design decisions.
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